TWR-56F8257 Freescale Semiconductor, TWR-56F8257 Datasheet - Page 31

• Manufacturer Part Number: TWR-56F8257
• Description: TOWER SYSTEM KIT MC56F8257
• Manufacturer: Freescale Semiconductor
• Type: DSC, Digital Signal Controllerr

Specifications of TWR-56F8257

• Contents: Board, Cables, Documentation, DVD
• For Use With/related Products: Freescale Tower System, MC56F8257
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3
The MC56F825x/MC56F824x series contains dual access memory. It can be accessed from core primary data buses (XAB1,
CDBW, CDBR) and secondary data buses (XAB2, XDB2). Addresses in data memory are selected on the XAB1 and XAB2
buses. Byte, word, and long data transfers occur on the 32-bit CDBR and CDBW buses. A second 16-bit read operation can be
performed in parallel on the XDB2 bus.
Peripheral registers and on-chip JTAG/EOnCE controller registers are memory mapped into data memory access. A special
direct address mode is supported for accessing a first 64-location in data memory by using a single word instruction.
The data memory map appears in
Freescale Semiconductor
1
2
1
2
All addresses are 16-bit word addresses.
This RAM is shared with data space starting at address X: 0x00 0000. See
All addresses are 16-bit word addresses.
This RAM is shared with data space starting at address X: 0x00 0000. See
Data Map
Begin/End Address
P: 0x1F FFFF
P: 0x00 8BFF
P: 0x00 7FFF
P: 0x00 8800
P: 0x00 8000
P: 0x00 2000
P: 0x00 2000
P: 0x00 0000
1
All addresses are 16-bit word addresses.
Begin/End Address
X:0xFF FEFF
X:0xFF FFFF
X:0xFF FF00
X:0x00 FFFF
X:0x00 EFFF
X:0x00 8FFF
X:0x00 7FFF
X:0x00 0FFF
X:0x01 0000
X:0x00 F000
X:0x00 9000
X:0x00 8000
X:0x00 1000
X:0x00 0000
Table 10. 56F8247 and 56F8255/56/57 Data Memory Map
Table 9. Program Memory Map
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Table 10
RESERVED
On-chip RAM
RESERVED
• Internal program flash: 48 KB
• Interrupt vector table locates from 0x00 2000 to 0x00 2085
• COP reset address = 0x00 2002
• Boot location = 0x00 2000
and
Table
2
: 6 KB
11.
EOnCE
256 locations allocated
RESERVED
On-chip peripherals
4096 locations allocated
RESERVED
On-chip data RAM alias
RESERVED
On-chip data RAM
8 KB
2
1
Memory Allocation
for 56F8245/46 at Reset
Memory Allocation
Figure
Figure
7.
7.
1
Memory Maps
31