TWR-56F8257 Freescale Semiconductor, TWR-56F8257 Datasheet - Page 46

• Manufacturer Part Number: TWR-56F8257
• Description: TOWER SYSTEM KIT MC56F8257
• Manufacturer: Freescale Semiconductor
• Type: DSC, Digital Signal Controllerr

Specifications of TWR-56F8257

• Contents: Board, Cables, Documentation, DVD
• For Use With/related Products: Freescale Tower System, MC56F8257
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Features
State of PWM2_EXTB:
5.8
The 56800E family includes extensive integrated support for application software development and real-time debugging. Two
modules, the Enhanced On-Chip Emulation (EOnCE) module and the core test access port (TAP, commonly called the JTAG
port), work together to provide these capabilities. Both are accessed through a common 4-pin JTAG/EOnCE interface. These
modules allow you to insert the MC56F825x/MC56F824x into a target system while retaining debug control. This capability is
especially important for devices without an external bus, because it eliminates the need for a costly cable to bring out the
footprint of the chip, as is required by a traditional emulator system.
The 56800E’s EOnCE module is a Freescale-designed module for developing and debugging application software used with
the chip. This module allows non-intrusive interaction with the CPU and is accessible through the pins of the JTAG interface
or by software program control of the 56800E core. Among the many features of the EOnCE module is support, in real-time
program execution, for data communication between the controller and the host software development and debug systems.
Other features allow for hardware breakpoints, the monitoring and tracking of program execution, and the ability to examine
and modify the contents of registers, memory, and on-chip peripherals, all in a special debug environment. No user-accessible
resources must be sacrificed to perform debugging operations.
The 56800E’s JTAG port provides an interface for the EOnCE module to the JTAG pins. The Joint Test Action Group (JTAG)
boundary scan is an IEEE 1149.1 standard methodology enabling access to test features using a test access port (TAP). A JTAG
boundary scan consists of a TAP controller and boundary scan registers. Contact your Freescale sales representative or
authorized distributor for device-specific BSDL information.
6
The MC56F825x/MC56F824x offers security features intended to prevent unauthorized users from gaining access to and
reading the contents of the flash memory (FM) array. The MC56F825x/MC56F824x’s flash memory security consists of several
hardware interlocks.
After flash memory security is set, the application software can allow an authorized user to access on-chip memory by including
a user-defined software subroutine that reads and transfers the contents of internal memory via peripherals. This application
software can communicate over a serial port, for example, to validate the authenticity of the requested access and then to grant
it until the next device reset. The system designer must use discretion when deciding whether to support this type of “back door”
access technique.
6.1
After you have programmed flash with the application code, or as part of programming the flash with the application code, you
can secure the MC56F825x/MC56F824x by programming the values 1 and 0 into bits 1 and 0, respectively, of program memory
location 0x00_7FF7. The CodeWarrior IDE menu flash lock command can also accomplish this task. The nonvolatile security
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If the ADC conversion result in SAMPLE1 is less than the value programmed into the low limit register 1,
PWM1_EXTB is driven high.
If the ADC conversion result in SAMPLE2 is greater than the value programmed into the high limit register 2,
PWM2_EXTB is driven low.
If the ADC conversion result in SAMPLE2 is less than the value programmed into the low limit register 2,
PWM2_EXTB is driven high.
Joint Test Action Group (JTAG)/Enhanced On-Chip Emulator
(EOnCE)
Security Features
Operation with Security Enabled
In normal operation, an external pullup on the TMS pin is highly recommend to place the
JTAG state machine in reset state (if this pin is not configured as GPIO).
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
NOTE
Freescale Semiconductor