CK-V6-ML623-G Xilinx Inc, CK-V6-ML623-G Datasheet
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CK-V6-ML623-G Summary of contents
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ML623 Virtex-6 FPGA GTX Transceiver Characterization Board User Guide UG724 (v1.1) September 15, 2010 ...
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit ...
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... System ACE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 System ACE Controller Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Configuration Address DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 JTAG Isolation Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 200 MHz 2.5V LVDS Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Single-Ended SMA Global Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Differential SMA Global Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SuperClock-2 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 User LEDs (Active High User DIP Switches (Active High User Push Buttons (Active High User Test I/O ...
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Appendix A: Default Jumper Positions Appendix B: VITA 57.1 FMC HPC Connector Pinout Appendix C: ML623 Master UCF Listing Appendix D: References 4 www.xilinx.com UG724 (v1.1) September 15, 2010 ML623 Board User Guide ...
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About This Guide This document describes the basic setup, features, and operation of the ML623 Virtex-6 FPGA GTX transceiver characterization board. The ML623 board provides the hardware environment for characterizing and evaluating the GTX transceivers available on the Virtex®-6 XC6VLX240T-2FFG1156C ...
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Preface: About This Guide Convention Courier font Courier bold Helvetica bold Italic font Online Document The following conventions are used in this document: Convention Blue text Blue, underlined text 6 Meaning or Use Messages, prompts, and program files that the ...
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... System ACE™ controller • Power module supporting all Virtex-6 FPGA GTX transceiver power requirements • A fixed, 200 MHz 2.5V LVDS oscillator wired to global clock inputs • Two single-ended global clock inputs with SMA connectors • Two pairs of differential global clock inputs with SMA connectors • ...
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... Transceiver and Transceiver Clock SMA GTX QUAD_112 Auxiliary Power Transceiver and On-board Regulation: Transceiver Clock SMA 5. Amps 3. Amps 2. Amps Figure 1-1: ML623 Board Block Diagram Detailed Description Figure 1-2 that is referenced in Note: The image in board. 8 FMC Interface FMC1 FMC2 FMC3 (ANSI/VITA 57.1-2008 v1.1) ...
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... MHz 2.5V LVDS oscillator (U7) 11 Single-ended SMA global clock input (J171, J172) 12 Differential SMA global clock inputs (J167, J166, J169, J170) SuperClock-2 module 14 User LEDs, active High (DS10 - DS17) 15 User DIP switches, active High (SW7) 16 User push buttons, active High (SW4, SW6) ...
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... ATX connector (J141) 1d: Power regulation jumpers (J30, J31, J33, J102, J104, J105) 1e: Regulation inhibit (J14, J19) 1f: External power supply jacks (J98, J173, J174, J175, J177, J178, J189, J220, J223, J227, J234) 1g: TI PMBus cable connector (J6) 1h: GTX transceiver power supply module ...
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... Switching Module PTD08A020W 3.3V at 20A max PTV12010WAD DC-DC Converter 5. max Figure 1-3: ML623 Board Power Supply Block Diagram The ML623 board uses power regulators and PMBus compliant digital PWM system controllers from Texas Instruments to supply the core and auxiliary voltages listed in Table 1-1 ...
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... Each power rail has a corresponding jack and jumper that is used to supply voltage to the rail using an external power supply. The jack, jumper, and regulator for each power rail is ...
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... MGTAVCC 1.025V 20A MGTAVTT 1.2V 12A The GTX transceiver power rails also have corresponding input voltage jacks to supply each voltage independently from a bench-top power supply (See External Supply Jack column in ML623 Board User Guide UG724 (v1.1) September 15, 2010 Figure Figure 1-4: Mounting Location, GTX Transceiver Power Module ...
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... Note: The power regulation jumper must be placed in the OFF position before connecting an external supply to its corresponding supply jack. The Texas Instruments and Intersil modules do not have voltage regulation jumpers and must be removed from the board before providing external power to the GTX transceiver rails ...
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X-Ref Target - Figure 1-5 J1 JTAG Cable Connector FPGA System ACE Controller CFGTDI TDO CFGTDO TDI U1 U25 PROG Push Button [Figure 1-2, callout 3] Pressing the PROG push button (SW5) grounds the active-Low program pin of the FPGA. ...
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... The onboard System ACE controller (U25) allows storage of multiple configuration files on a CompactFlash card. These configuration files can be used to program the FPGA. The CompactFlash card connects to the CompactFlash card connector (U24) located directly below the System ACE controller on the back side of the board. System ACE Controller Reset [Figure 1-2, callout 7] Pressing push button SW2 (RESET) resets the System ACE controller ...
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... The ML623 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the FPGA global clock inputs. The 200 MHz differential clock is enabled by placing two shunts (P, N) across J188 header pins 1 – 3 and 2 – 4 (LVDS). Table 1-5: LVDS Oscillator Global Clock Connections ...
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... The SuperClock-2 module connects to the clock module interface connector (J32) and provides a programmable, low-noise clock source for the ML623 board. The clock module maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock pair, and 1 reset pin. Table 1-8 The ML623 board also supplies 5V, 3 ...
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... Table 1-8: SuperClock-2 FPGA I/O Mapping (Cont’d) FPGA Pin K22 K21 A19 A18 J22 H22 D19 E19 E21 D21 H20 H19 A20 E23 E22 B22 B21 J21 J20 C23 B23 G22 G21 User LEDs (Active High) [Figure 1-2, callout 14] ...
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Chapter 1: ML623 Board Features and Operation Table 1-9: User LEDs (Cont’d) FPGA Pin F15 G15 B15 A15 G16 F16 User DIP Switches (Active High) [Figure 1-2, callout 15] The DIP switch SW7 provides a set of eight active-High switches ...
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... All FPGA GTX transceiver pins are connected to differential SMA connector pairs. The GTX transceivers are grouped into five sets of four (referred to as Quads) which share two differential reference clock pin pairs corresponding SMA connector are shown in ML623 Board User Guide UG724 (v1 ...
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... Chapter 1: ML623 Board Features and Operation X-Ref Target - Figure 1-7 QUAD_113 QUAD_112 Figure 1-7: GTX Transceiver and Reference Clock SMA Locations Table 1-13: GTX Transceiver Pins FPGA Pin AP5 AP6 AP1 AP2 AM5 AM6 AN3 AN4 AL3 AL4 22 QUAD_114 QUAD_115 116 Clocks ...
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Table 1-13: GTX Transceiver Pins (Cont’d) FPGA Pin AM1 AM2 AJ3 AJ4 AK1 AK2 AG3 AG4 AH1 AH2 AF5 AF6 AF1 AF2 AE3 AE4 AD1 AD2 AC3 AC4 AB1 AB2 AA3 AA4 ...
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Chapter 1: ML623 Board Features and Operation Table 1-13: GTX Transceiver Pins (Cont’d) FPGA Pin ...
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... The ML623 board provides differential SMA connectors that can be used for connecting an external function generator to all GTX transceiver reference clock inputs of the FPGA. The FPGA reference clock pins are connected to the SMA connectors as shown in Table 1-14: GTX Transceiver Clock Inputs to the FPGA ...
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Chapter 1: ML623 Board Features and Operation USB to UART Bridge [Figure 1-2, callout 20] Communications between the ML623 board and a host computer are through a USB cable connected to J9. Control is provided by U26, a USB to ...
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... The ML623 board features three high pin count (HPC) connectors as defined by the VITA 57.1.1 FMC specification. The FMC HPC connector position socket that is fully populated with 400 pins. See cross-reference of signal names to pin coordinates. ...
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Chapter 1: ML623 Board Features and Operation Table 1-18: VITA 57.1 FMC1 HPC Connections at J112 (Cont’d) FPGA Pin AD27 AH33 AH32 AE28 AE29 AJ34 AH34 AF28 AF29 AL34 AK34 AH29 AH30 AF26 AE26 AJ31 AJ32 AJ29 AJ30 AK33 AK32 ...
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Table 1-18: VITA 57.1 FMC1 HPC Connections at J112 (Cont’d) FPGA Pin AB25 AC25 AA30 AA31 AA34 AA33 N28 N29 M31 L31 N25 M25 M26 M27 P31 P30 N27 P27 N32 P32 L33 M32 L28 M28 R28 R27 R31 R32 ...
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Chapter 1: ML623 Board Features and Operation Table 1-18: VITA 57.1 FMC1 HPC Connections at J112 (Cont’d) FPGA Pin N30 N34 P34 P29 R29 L29 L30 F33 G33 C32 B32 J26 J27 L25 L26 J31 J32 U27.9 U27.8 AD30 AC30 ...
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Table 1-18: VITA 57.1 FMC1 HPC Connections at J112 (Cont’d) FPGA Pin AA28 AA29 AE33 AF33 AD29 AC29 AB32 AC32 AB28 AC28 AD32 AE32 AB27 AC27 AG33 AG32 AA26 AB26 AG31 AF31 V34 W34 V28 V27 U25 T25 T28 T29 ...
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... FMC1_LA28_N H31 FMC1_LA29_P G31 FMC1_LA29_N G30 FMC1_LA30_P H35 FMC1_LA30_N H34 FMC1_LA31_P G34 FMC1_LA31_N G33 FMC1_LA32_P H38 FMC1_LA32_N H37 FMC1_LA33_P G37 FMC1_LA33_N G36 FMC1_PRSNT_M2C_L H2 (1) FMC1_TCK_BUF D29 (1) FMC1_TDI D30 (1) FMC1_TDO D31 (1) TMS_BUF D33 www.xilinx.com ML623 Board User Guide UG724 (v1.1) September 15, 2010 ...
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Table 1-19: VITA 57.1 FMC2 HPC Connections at J113 FPGA Pin K13 K12 J25 J24 C29 D29 F19 F20 AP20 AP21 AF19 AE19 AE21 AD21 AM18 AL18 AG22 AH22 AP19 AN18 AK22 AJ22 AN19 AN20 AC20 AD20 AM20 AL20 AF20 ...
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Chapter 1: ML623 Board Features and Operation Table 1-19: VITA 57.1 FMC2 HPC Connections at J113 (Cont’d) FPGA Pin AL21 AC19 AD19 AM23 AL23 AK21 AJ21 AM22 AN22 AK19 AL19 AG20 AG21 AP22 AN23 AP25 AP24 AN30 AM30 AH27 AH28 ...
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Table 1-19: VITA 57.1 FMC2 HPC Connections at J113 (Cont’d) FPGA Pin D24 E24 B26 A26 G26 G27 B27 C27 H27 G28 A28 A29 F28 E28 A30 B30 E29 F29 C30 D30 F25 G25 F21 G20 C20 D20 A23 A24 ...
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Chapter 1: ML623 Board Features and Operation Table 1-19: VITA 57.1 FMC2 HPC Connections at J113 (Cont’d) FPGA Pin U27.10 AN27 AM27 AH25 AJ25 AG25 AG26 AP30 AP31 AL29 AK29 AN29 AP29 AL28 AK28 AN28 AM28 AK27 AJ27 AH23 AH24 ...
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Table 1-19: VITA 57.1 FMC2 HPC Connections at J113 (Cont’d) FPGA Pin AK23 AL24 U23 V23 AD24 AE24 M23 L24 F24 F23 N23 N24 H23 G23 R24 P24 H25 H24 T24 T23 V24 W24 AF25 AF24 Y24 AA24 AF23 AG23 ...
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... AC15 AD15 AH17 AG17 AG15 AF15 AK14 AJ14 AJ15 AH15 AL15 38 Net Name FMC Pin FMC2_LA32_N H38 FMC2_LA33_P G36 FMC2_LA33_N G37 FMC2_PRSNT_M2C_L H2 (1) FMC2_TCK_BUF D29 (1) FMC2_TDI D30 (1) FMC2_TDO D31 (1) TMS_BUF D33 Net Name FMC Pin FMC3_CLK0_M2C_P H4 FMC3_CLK0_M2C_N H5 FMC3_CLK1_M2C_P G2 FMC3_CLK1_M2C_N G3 FMC3_CLK2_M2C_P K4 FMC3_CLK2_M2C_N ...
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Table 1-20: VITA 57.1 FMC3 HPC Connections at J115 (Cont’d) FPGA Pin AL14 AG16 AF16 AN15 AM15 AJ17 AJ16 AP16 AP15 AC18 AC17 AH18 AG18 AN17 AP17 AJ19 AH19 AM17 AM16 AD17 AE17 AK18 AK17 AE16 AD16 AE18 AF18 AL16 ...
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Chapter 1: ML623 Board Features and Operation Table 1-20: VITA 57.1 FMC3 HPC Connections at J115 (Cont’d) FPGA Pin AE13 AE12 L13 M13 G13 H14 D14 C14 A13 A14 G12 H13 F14 E14 K14 J14 H10 G10 B12 B13 C13 ...
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Table 1-20: VITA 57.1 FMC3 HPC Connections at J115 (Cont’d) FPGA Pin E12 M12 M11 L15 L14 F18 E17 E18 D17 H15 J15 D15 C15 U27.14 U27.13 AC13 AC12 AJ10 AH10 AD14 AC14 AK12 AJ12 AF11 AE11 AM10 AL10 AG11 ...
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Chapter 1: ML623 Board Features and Operation Table 1-20: VITA 57.1 FMC3 HPC Connections at J115 (Cont’d) FPGA Pin AP11 AP12 AF13 AG13 AM12 AN12 AE14 AF14 AN13 AM13 AG12 AH12 AK13 AL13 AH13 AH14 AC10 AB10 AH9 AJ9 F9 ...
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... G30 FMC3_LA29_N G31 FMC3_LA30_P H34 FMC3_LA30_N H35 FMC3_LA31_P G33 FMC3_LA31_N G34 FMC3_LA32_P H37 FMC3_LA32_N H38 FMC3_LA33_P G36 FMC3_LA33_N G37 FMC3_PRSNT_M2C_L H2 (1) FMC3_TCK_BUF D29 (1) FMC3_TDI D30 (1) FMC3_TDO D31 (1) TMS_BUF D33 Allowable Number Maximum Voltage Range of Pins Amps Fixed 2.5V 4 3.3V 1 0.020 3.3V ...
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... The I C bus is controlled through U27, an 8-channel I Semiconductor PCA9547). The FPGA communicates with the multiplexer through I data and clock signals mapped to FPGA pins H34 and H33, respectively. The I the PCA9547 device is 0x70. The bus hosts five components: • SuperClock-2 module • ...
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... Default Jumper Positions Table A-1 shows the 27 standard (black) shunts that must be installed on the board for proper operation. There are an additional 5 (red) shorting plugs that must be installed to enable the output of on-board, digitally-controlled power always be installed except where specifically noted in this user guide. Refer to PCB Assembly Drawing 0431511 for the default placement of all on-board jumpers and their respective connectors as they are located on the board ...
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Appendix A: Default Jumper Positions Table A-1: Standard Shunts (Cont’d) Connector Name (1) J182 VREF SELECT J36 FMC1 JTAG J37 FMC2 JTAG J38 FMC3 JTAG Notes: Italicized entries in the Name column are not visible in the PCB silkscreen labels. ...
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... LA18_N_CC GND DP1_C2M_N LA23_N GND DP9_C2M_P GND GND DP9_C2M_N LA26_P LA27_P GND DP2_C2M_P LA26_N LA27_N GND DP2_C2M_N GND GND DP8_C2M_P TCK GND DP8_C2M_N TDI SCL GND DP3_C2M_P TDO SDA GND DP3_C2M_N 3P3VAUX GND DP7_C2M_P TMS GND DP7_C2M_N TRST_L GA0 GND DP4_C2M_P ...
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Appendix B: VITA 57.1 FMC HPC Connector Pinout 48 www.xilinx.com UG724 (v1.1) September 15, 2010 ML623 Board User Guide ...
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ML623 Master UCF Listing The ML623 master user constraints file (UCF) template provides for designs targeting the ML623 Virtex-6 FPGA GTX transceiver characterization board. Net names in the constraints listed below correlate with net names on the ML623 board schematic. ...
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Appendix C: ML623 Master UCF Listing NET "113_RX3_P" NET "113_TX0_N" NET "113_TX0_P" NET "113_TX1_N" NET "113_TX1_P" NET "113_TX2_N" NET "113_TX2_P" NET "113_TX3_N" NET "113_TX3_P" NET "114_REFCLK0_N" NET "114_REFCLK0_P" NET "114_REFCLK1_N" NET "114_REFCLK1_P" NET "114_RX0_N" NET "114_RX0_P" NET "114_RX1_N" NET "114_RX1_P" ...
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NET "116_RX3_N" NET "116_RX3_P" NET "116_TX0_N" NET "116_TX0_P" NET "116_TX1_N" NET "116_TX1_P" NET "116_TX2_N" NET "116_TX2_P" NET "116_TX3_N" NET "116_TX3_P" NET "CCLK_0" NET "CLK_A" NET "CLK_B" NET "CLK_DIFF_A_N" NET "CLK_DIFF_A_P" NET "CLK_DIFF_B_N" NET "CLK_DIFF_B_P" NET "CM_CTRL_0" NET "CM_CTRL_1" NET "CM_CTRL_10" ...
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... Appendix C: ML623 Master UCF Listing NET "DUT_SPI_CS" NET "DUT_SPI_D" NET "DUT_SPI_Q" NET "DUT_SPI_SCK" NET "FMC1_CLK0_M2C_N" NET "FMC1_CLK0_M2C_P" NET "FMC1_CLK1_M2C_N" NET "FMC1_CLK1_M2C_P" NET "FMC1_CLK2_M2C_N" NET "FMC1_CLK2_M2C_P" NET "FMC1_CLK3_M2C_N" NET "FMC1_CLK3_M2C_P" NET "FMC1_HA00_CC_N" NET "FMC1_HA00_CC_P" NET "FMC1_HA01_CC_N" NET "FMC1_HA01_CC_P" NET "FMC1_HA02_N" NET "FMC1_HA02_P" ...
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NET "FMC1_HB00_CC_P" NET "FMC1_HB01_N" NET "FMC1_HB01_P" NET "FMC1_HB02_N" NET "FMC1_HB02_P" NET "FMC1_HB03_N" NET "FMC1_HB03_P" NET "FMC1_HB04_N" NET "FMC1_HB04_P" NET "FMC1_HB05_N" NET "FMC1_HB05_P" NET "FMC1_HB06_CC_N" NET "FMC1_HB06_CC_P" NET "FMC1_HB07_N" NET "FMC1_HB07_P" NET "FMC1_HB08_N" NET "FMC1_HB08_P" NET "FMC1_HB09_N" NET "FMC1_HB09_P" NET "FMC1_HB10_N" ...
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Appendix C: ML623 Master UCF Listing NET "FMC1_LA08_N" NET "FMC1_LA08_P" NET "FMC1_LA09_N" NET "FMC1_LA09_P" NET "FMC1_LA10_N" NET "FMC1_LA10_P" NET "FMC1_LA11_N" NET "FMC1_LA11_P" NET "FMC1_LA12_N" NET "FMC1_LA12_P" NET "FMC1_LA13_N" NET "FMC1_LA13_P" NET "FMC1_LA14_N" NET "FMC1_LA14_P" NET "FMC1_LA15_N" NET "FMC1_LA15_P" NET "FMC1_LA16_N" ...
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NET "FMC2_CLK3_M2C_N" NET "FMC2_CLK3_M2C_P" NET "FMC2_HA00_CC_N" NET "FMC2_HA00_CC_P" NET "FMC2_HA01_CC_N" NET "FMC2_HA01_CC_P" NET "FMC2_HA02_N" NET "FMC2_HA02_P" NET "FMC2_HA03_N" NET "FMC2_HA03_P" NET "FMC2_HA04_N" NET "FMC2_HA04_P" NET "FMC2_HA05_N" NET "FMC2_HA05_P" NET "FMC2_HA06_N" NET "FMC2_HA06_P" NET "FMC2_HA07_N" NET "FMC2_HA07_P" NET "FMC2_HA08_N" NET "FMC2_HA08_P" ...
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Appendix C: ML623 Master UCF Listing NET "FMC2_HB05_P" NET "FMC2_HB06_CC_N" NET "FMC2_HB06_CC_P" NET "FMC2_HB07_N" NET "FMC2_HB07_P" NET "FMC2_HB08_N" NET "FMC2_HB08_P" NET "FMC2_HB09_N" NET "FMC2_HB09_P" NET "FMC2_HB10_N" NET "FMC2_HB10_P" NET "FMC2_HB11_N" NET "FMC2_HB11_P" NET "FMC2_HB12_N" NET "FMC2_HB12_P" NET "FMC2_HB13_N" NET "FMC2_HB13_P" ...
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NET "FMC2_LA13_N" NET "FMC2_LA13_P" NET "FMC2_LA14_N" NET "FMC2_LA14_P" NET "FMC2_LA15_N" NET "FMC2_LA15_P" NET "FMC2_LA16_N" NET "FMC2_LA16_P" NET "FMC2_LA17_CC_N" NET "FMC2_LA17_CC_P" NET "FMC2_LA18_CC_N" NET "FMC2_LA18_CC_P" NET "FMC2_LA19_N" NET "FMC2_LA19_P" NET "FMC2_LA20_N" NET "FMC2_LA20_P" NET "FMC2_LA21_N" NET "FMC2_LA21_P" NET "FMC2_LA22_N" NET "FMC2_LA22_P" ...
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Appendix C: ML623 Master UCF Listing NET "FMC3_HA04_N" NET "FMC3_HA04_P" NET "FMC3_HA05_N" NET "FMC3_HA05_P" NET "FMC3_HA06_N" NET "FMC3_HA06_P" NET "FMC3_HA07_N" NET "FMC3_HA07_P" NET "FMC3_HA08_N" NET "FMC3_HA08_P" NET "FMC3_HA09_N" NET "FMC3_HA09_P" NET "FMC3_HA10_N" NET "FMC3_HA10_P" NET "FMC3_HA11_N" NET "FMC3_HA11_P" NET "FMC3_HA12_N" ...
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NET "FMC3_HB10_P" NET "FMC3_HB11_N" NET "FMC3_HB11_P" NET "FMC3_HB12_N" NET "FMC3_HB12_P" NET "FMC3_HB13_N" NET "FMC3_HB13_P" NET "FMC3_HB14_N" NET "FMC3_HB14_P" NET "FMC3_HB15_N" NET "FMC3_HB15_P" NET "FMC3_HB16_N" NET "FMC3_HB16_P" NET "FMC3_HB17_CC_N" NET "FMC3_HB17_CC_P" NET "FMC3_HB18_N" NET "FMC3_HB18_P" NET "FMC3_HB19_N" NET "FMC3_HB19_P" NET "FMC3_HB20_N" ...
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Appendix C: ML623 Master UCF Listing NET "FMC3_LA18_CC_N" NET "FMC3_LA18_CC_P" NET "FMC3_LA19_N" NET "FMC3_LA19_P" NET "FMC3_LA20_N" NET "FMC3_LA20_P" NET "FMC3_LA21_N" NET "FMC3_LA21_P" NET "FMC3_LA22_N" NET "FMC3_LA22_P" NET "FMC3_LA23_N" NET "FMC3_LA23_P" NET "FMC3_LA24_N" NET "FMC3_LA24_P" NET "FMC3_LA25_N" NET "FMC3_LA25_P" NET "FMC3_LA26_N" ...
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NET "USB_GPIO0" NET "USB_GPIO1" NET "USB_GPIO2" NET "USB_GPIO3" NET "USB_RTS" NET "USB_RX" NET "USB_TX" ML623 Board User Guide UG724 (v1.1) September 15, 2010 LOC = "J29"; LOC = "K28"; LOC = "B34"; LOC = "C33"; LOC = "E33"; LOC = ...
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Appendix C: ML623 Master UCF Listing 62 www.xilinx.com UG724 (v1.1) September 15, 2010 ML623 Board User Guide ...
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... UG361, Virtex-6 FPGA SelectIO Resources User Guide • UG362, Virtex-6 FPGA User Guide: Clocking Resources • UG364, Virtex-6 FPGA Configurable Logic Block User Guide • UG365, Virtex-6 FPGA Packaging and Pinout Specifications • UG366, Virtex-6 FPGA GTX Transceivers User Guide • ...
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Appendix D: References 64 www.xilinx.com UG724 (v1.1) September 15, 2010 ML623 Board User Guide ...