ATA5749-EK2 Atmel, ATA5749-EK2 Datasheet - Page 6

• Manufacturer Part Number: ATA5749-EK2
• Description: BOARD EVALUATION TPMS 433MHZ
• Manufacturer: Atmel
• Type: Transmitterr

Specifications of ATA5749-EK2

• Frequency: 433MHz
• For Use With/related Products: ATA5749
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3
3.4
6
Crystal Oscillator
Clock Driver
Atmel ATA5749
The crystal oscillator (XTO) is an amplitude-regulated Pierce oscillator. It has fixed function and
is not programmable. The oscillator is enabled when the EN is “set”. After the oscillator’s output
amplitude reaches an acceptable level, the XTO_RDY flag is “set”. The CLK-pin becomes active
if CLK_ON is set. The PLL receives its reference frequency.
Typically, this process takes about 200µs when using a small sized crystal with a motional
capacitance of 4fF. This start-up time strongly depends on the motional capacitance of the
crystal and is lower with higher motional capacitance.
The high negative starting impedance of R
failure rate due to the “sleeping crystal” phenomena (more common among very small sized
3.2mm
The clock driver block shown in
CLK_ON, and DIV_CNTRL bits in the configuration register. When CLK_ONLY is “clear”, normal
operation is selected and the fractional-N PLL is operating. When CLK_ON is “set”, the CLK
output is enabled. The crystal clock divider ratio can be set to divide by four when DIV_CNTRL is
“set” and divide by eight when DIV_CNTRL is “clear”. With a 13.0000MHz crystal, this yields an
output of 3.25MHz or 1.625MHz, respectively. When CLK_ON is “clear”, no clock is available at
CLK and the transmitter has less current consumption.
The CLK signal can be used to clock a microcontroller. It is CMOS compatible and can drive up
to 20pF of load capacitance at 1.625MHz and up to 10pF at 3.25MHz. When the device is in
power-down mode, the CLK output stays low. Upon power up, CLK output remains low until the
amplitude detector of the crystal oscillator detects sufficient amplitude and XTO_RDY and
CLK_ON are “set”. After this takes place, CLK output becomes active. The CLK output is
synchronized with the XTO_RDY signal so that the first period of the CLK output is always a full
period (no CLK output spike at activation).
To lower overall current consumption, it is possible to power down the entire chip except for the
crystal oscillator block. This can be achieved when the CLK_ONLY is “set”.
2.5mm crystals).
Figure 1-1 on page 2
XTO12_START
is programmed using the CLK_ONLY,
> 1500 is important to minimize the
9128G–RKE–03/11