RX5000 RFM, RX5000 Datasheet - Page 9

• Manufacturer Part Number: RX5000
• Description: ASH RX 115.2 KBPS 433.92 MHZ
• Manufacturer: RFM
• Type: Receiverr

Specifications of RX5000

• Frequency: 433.92MHz
• Sensitivity: -109dBm
• Data Rate - Maximum: 115.2kbps
• Modulation Or Protocol: ASK, OOK
• Applications: General Data Transfer
• Current - Receiving: 3.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 3.7 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: SM-20L
• Operating Frequency: 434.12 MHz
• Operating Supply Voltage: 2.5 V or 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 3 mA
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 583-1074-2

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©2008 by RF Monolithics, Inc.
Pin
10
12
13
14
15
16
17
18
19
20
11
PWIDTH
CNTRL1
CNTRL0
PRATE
THLD2
THLD1
Name
E-mail: [e-mail]
GND2
RREF
GND3
VCC2
RFIO
GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%
resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less
than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less
that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF.
THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor R
between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak detector value
(increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB below peak, or 60 mV for
a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by:
A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the dB-below-peak
data slicer operation.
The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R
increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The value of the
resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the acceptable range for the resistor is 0
to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:
For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a THLD1 range
of 0 to 90 mV. The resistor value is given by:
A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required for proper
AGC operation.
The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the
first RF amplifier t
5 µs with a resistor in the range of 51 K to 2000 K. The value of R
A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers
operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period t
of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K
to 220 K. In this case the value of R
A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional
amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than 5
pF to maintain stability.
The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t
width to the second RF amplifier t
can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of R
A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at
a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by
the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to
less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor
between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode.
VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which
may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor.
CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode.
CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS
compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is inter-
preted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a
maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic
level; it cannot be left unconnected.
CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compatible). An
input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic
high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source
current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left
unconnected.
GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an imped-
ance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and a shunt
matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some imped-
ances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection.
R
R
R
R
R
R
TH2
TH1
TH1
PR
PR
PW
= 404* t
= 198* t
= 404* t
= 1.67*V, where R
= 1.11*V, where R
= 2.22*V, where R
PRI
PRI
PRC
PW1
is set by a resistor R
+ 10.5, where t
- 8.51, where t
- 18.6, where t
TH1
TH2
TH1
PW2
is in kilohms and the threshold V is in mV
is in kilohms and the threshold V is in mV
is in kilohms and the threshold V is in mV
PR
is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width t
PRI
is given by:
PRC
PW1
PR
is in µs, and R
is in µs and R
is in µs and R
between this pin and ground. The interval t
Description
PR
PR
PW
is in kilohms
is in kilohms
is in kilohms
PR
is given by:
PW1
with a resistor R
PRI
TH1
can be adjusted between 0.1 and
to RREF. The threshold is
PW
to ground (the ON pulse
PRC
from start-to-start
PW
is given by:
RX5000 - 4/7/08
Page 9 of 10
TH2
PW1