SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet
SI4322-A1-FT
Specifications of SI4322-A1-FT
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SI4322-A1-FT Summary of contents
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... FCC or ETSI conformance for unlicensed use in the 433, 868, and 915 MHz bands. Used in conjunction with Silicon Labs' FSK transmitters, the Si4322 is a flexible, low cost, and highly integrated solution that does not require production alignments. All required RF functions are integrated ...
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... Si4322 Functional Block Diagram MIX I 13 IN1 LNA IN2 12 MIX Q PLL & I/Q VCO with cal. RF Parts WTM CLK div Xosc with cal CLK XTL/REF 2 AMP OC Self cal. AMP OC RSSI COMP DQD BB Amp/Filt./Limiter LBD Controller Low Power parts ARSSI SCK nSEL SDO nIRQ SDI Rev ...
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... Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. FIFO Buffered Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1. Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 7.2. Interrupt Controlled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3. FIFO Read Example with FFIT Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8. Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9. Dual Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10. Wake-Up Timer Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11. RX-TX Alignment Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Rev. 1.2 Si4322 Page 3 ...
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... Reset modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 13.1. Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 13.2. Power Glitch Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 14. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15. Reference Design: Evaluation Board with 50 Matching Network . . . . . . . . . . . . . . 38 16. PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 17. Pin Descriptions—Si4322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 18. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 19. Package Outline: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 4 Rev. 1.2 ...
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... POR even above 2 the threshold V POR SR for proper POR generation Vdd 3 – Rev. 1.2 Si4322 Min Typ Max — — 0.3 — — — — 0.5 — 2.0 3.5 — ±2.5 — — 1.5 — — — 0.6 dd 0.1 — — — — — ...
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... Si4322 Table 2. AC Characteristics (Test conditions ° 2 Parameter Symbol Receiver Frequency f LO Receiver Bandwidth BW FSK Bit Rate BR FSK Bit Rate BRA Receiver Sensitivity P min AFC Locking Range AFC range Input IP3 IIP3 inh Input IP3 IIP3 outh Co-Channel Rejection CCR Blocking Ratio ...
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... After V has reached 90 final value 4 Crystal ESR < 50 16pF L 5 Calibrated every 30 seconds 15 pF pure capacitive load 10 pF pure capacitive load Tolerance ± 1 kHz Rev. 1.2 Si4322 Min Typ Max Units 1 — — nF — 6 — dB — 500 — ...
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... Si4322 Table 3. Recommended Operating Conditions Parameter Positive Supply Voltage Ambient Operating Temperature Table 4. Absolute Maximum Ratings Parameter Positive Supply Voltage Voltage on Any Pin Input Current into Any Pin Except VDD and VSS Electrostatic Discharge with Human Body Model Storage Temperature Lead Temperature (soldering, max 10 s) ...
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... 0603 Tantalum Ceramic Ceramic Pin 6 RX data output nFFS input (RX data FIFO can be accessed) Rev. 1.2 Si4322 VDD VDD C4 2.2 nF (opt PCB Antenna or matching network to 50 Ohm X1 10 MHz C3 C3 0603 Pin 7 RX data clock output FFIT output ...
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... Si4322 3. Internal Pin Connections Pin Name Internal Connection VDD 1 SDI 2 SCK PAD 1.5k 3 nSEL VSS VDD SDO 4 PAD 10 FFIT VSS VDD 5 nIRQ PAD 10 VSS VDD DATA 120k 6 PAD 10 nFFS VSS VDD DCLK 7 FFIT PAD 10 CFIL VSS VDD 8 CLK PAD 10 VSS 10 Pin Name ...
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... Functional Description The Si4322 FSK receiver is the counterpart of Silicon Labs’ Si4022 FSK transmitter. It covers the unlicensed frequency bands at 433, 868 and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. The receiver employs zero-IF approach with I/Q demodulation, allowing the use of a minimal number of external components in a typical application ...
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... Si4322 Digital operation: The data filter is a digital realization of an analog RC filter followed by a comparator with hysteresis. In this mode, there is a clock recovery circuit (CR), which can provide synchronized clock to the data. With this clock, the received data can fill the RX Data FIFO. The CR has three operation modes: fast, slow, and automatic ...
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... Configuration Setting Command" on page 16 or "5.5. Receiver Setting Command" on page 18). The Si4322 generates an interrupt signal on several events (wake-up timer timeout, low supply voltage detection, on-chip FIFO filled up). This signal can be used to wake up the microcontroller, effectively reducing the period the microcontroller has to be active ...
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... Si4322 5. Control Interface Commands to the receiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface ...
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... Bit rate FIFO IT level, FIFO start control, FIFO enable and FIFO fill enable Clock tail, wake-up auto calibration, PLL bandwidth, long FIFO IT level Receiver status read Rev. 1.2 Si4322 Related Control Bits b1 to b0, eb, et i0, dc f11 c0, m13 to m8 ...
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... Si4322 Table 6. Control Register Default Values 1 Configuration Setting Command 2 Frequency Setting Command 3 Receiver Setting Command 4 Synchron Pattern Command 5 Wake-up Timer Command 6 Extended Wake-up Timer Command 7 Low Duty-Cycle Command 8 Low Battery Detector and Clock Divider Command 9 AFC Control Command 10 Data Filter Command ...
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... It is possible to decrease the clock tail length to 128 pulses by clearing the ctls bit in "5.15. Extended Features Command" on page 26 Crystal Load Capacitance [ 10.0 …… … 15 16 Baseband Bandwidth [kHz Reserved 400 340 270 200 135 Reserved Reserved Rev. 1.2 Si4322 17 ...
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... Si4322 5.4. Frequency Setting Command Bit f11 f10 The 12-bit parameter F (bits f11 to f0) should be in the range of 96 and 3903. When F is out of range, the previous value is kept. The synthesizer center frequency f can be calculated as follows F/4000) [MHz] 0 Band Min Frequency 433 MHz 400 ...
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... Note: The wake-up timer generates interrupts continuously at the programmed interval while the et bit ("5.3. Configuration Set- ting Command" on page 16) is set (dB relative to maximum gain) LNA –6 0 –12 1 – RSSI [dBm] setth –103 – – – – – – – setth LNA – Rev. 1.2 Si4322 POR C1D4h POR E196h 19 ...
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... DQD signal may not go high even when the received sig- nal has good quality. There is an application proposal shown below. The Si4322 is configured to work in FIFO mode. The chip periodically wakes up and switches to receiving mode. If valid FSK data received, the chip sends an interrupt to the microcontroller and continues filling the RX FIFO ...
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... Bit 5:4 <rl1 : rl0>: Limit the value of the frequency offset register to the following values cd2 cd1 cd0 elfc cd2 cd1 cd0 Clock Output Frequency [MHz "5.3. Configuration Setting Command" on page rl1 rl0 rl1 rl0 Max dev [f ] res restriction 0 1 ± ± ±1 Rev. 1.2 Si4322 POR C213h ). of the POR aen C687h 21 ...
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... Si4322 f : res 434MHz band: 10 kHz 868MHz band: 20 kHz 915MHz band: 20 kHz Bit 7:6 <a1 : a0>: Automatic operation mode selector BASEBAND SIGNAL IN 0 10MHz CLK. M CLK FINE fi (bit2) ENABLE CALCULATION en (bit0) VDI* AUTO OPERATION au (bit6,7) Power -on reset (POR) rl1, 0 (bit4,5) st (bit 3) oe (bit1) F< ...
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... Note: Bit rate cannot exceed 115 kbps in this mode dsfi sf "5.13. Data Rate Command" on page 24 sf Filter Type 0 Digital filter 1 Analog RC filter "5.13. Data Rate Command" on page 24 Rev. 1.2 Si4322 POR ewi C462h ). . 23 ...
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... Si4322 Analog RC filter: The demodulator output is fed to pin 7 over a 10 k resistor. The filter cut-off frequency is set by the external capacitor connected to this pin and VSS. The table shows the optimal filter capacitor values for different data rates. Data Rate [kbps] 1.2 ...
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... Sync . W ord X logic HIGH 3 Detector EN nRES s0* s1* Pad DATA I/ O Port fifo enable* DIRECTION NOTE: * For details see the FIFO Settings Command "5.5. Receiver Setting Command" on page 18 Rev. 1.2 Si4322 POR CE87h FIFO W RITE Logic (simplified) FIFO _WRITE_DATA FIFO _WRITE_CLK FIFO_WRITE_EN nFIFO_RESET ...
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... The read command starts with a zero, whereas all other control commands start with a one. Therefore, after receiving the first bit of the control command the Si4322 identifies read command. Therefore, as the first bit of the command is received, the receiver starts to clock out the status bits on the SDO output as follows: ...
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... Clock recovery lock ATGL Toggling in each AFC cycle ASAME AFC measured twice the same result OFFS(6) MSB of the measured frequency offset (sign of the offset value) OFFS(4)–OFFS(0) Offset value to be added to the value of the selected center frequency Function Rev. 1.2 Si4322 27 ...
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... Data Filter Command" on page 23. In this case the crystal oscillator will start and the Si4322 will not go to low current sleep mode if any interrupt remains active regardless to the state of the ex (enable crystal oscillator) bit in the "5.3. Configuration Setting Command" on page 16. This way the microcontroller always can have clock signal to process the interrupt ...
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... FIFO read out FIFO OUT FO+1 FO+2 FO+3 FO+4 NOTE: *nFFS selects FIFO read mode /4, where f is the crystal oscillator frequency. When the duty-cycle ref ref Rev. 1.2 Si4322 . ref 29 ...
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... Si4322 8. Power Saving Modes The different operating modes of the chip depend on the following control bits: Operating Mode Active Idle Sleep Standby *Note: Maximum value. eb, et, ex bits—"5.3. Configuration Setting Command" on page 16 elfc bit—"5.10. Low Battery Detector and Microcontroller Clock Divider Command" on page 21 en bit— ...
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... AFC has to be disabled during the read by clearing the aen bit in the "5.11. AFC Command" on page 21. T slow T slow x ) half cycle. The other is that both clocks should be up and running for the x Rev. 1.2 Si4322 clock periods are not to scale T fast 31 ...
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... Si4322 12. Crystal Selection Guidelines The crystal oscillator of the Si4322 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can variety of crystal types can be used ...
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... Transmitter Deviation [± kHz 100 120 100 Transmitter Deviation [± kHz 100 120 100 Transmitter Deviation [± kHz 100 120 Transmitter Deviation [± kHz 100 120 Rev. 1.2 Si4322 140 160 100 100 140 160 133 156 140 160 100 100 140 160 ...
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... Si4322 13. Reset modes The chip will enter into reset mode if any of the following conditions are met: Power-on reset: During a power up sequence until the V Power glitch reset: Transients present on the V Software reset: Special control command received by the chip 13.1. Power-On Reset After power up the supply voltage starts to rise from 0 V ...
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... SW Reset Command—Issuing FF00h command will trigger software reset (sensitive reset mode must be enabled). Reset threshold voltage (600mV) Reset ramp line Reset threshold voltage (600mV) Figure 9. Sensitive Reset Disabled Rev. 1.2 Si4322 (100mV/ms) time DD Reset ramp line (100mV/ms) time in the DC – 50 kHz range for PP ...
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... Si4322 14. Typical Performance Characteristics Figure 10. Channel Selectivity and Blocking Notes: LNA gain: maximum, filter bandwidth: 135 kHz, data rate: 9.6 kbps, AFC: switched off, FSK deviation: ±60 kHz, V The measurement was done according to the descriptions in the ETSI Standard EN 300 220-2 v.2.1.2 (2007-06), section ...
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... BW=135 kHz BW=135 kHz BW=135 kHz f f f =60 kHz =60 kHz =100 kHz FSK FSK FSK Rev. 1.2 Si4322 115 kbps -90 -85 115 kbps -90 -85 ) FSK 57.6 kbps 115.2 kbps BW=200 kHz BW=270 kHz f f =120 kHz ...
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... Si4322 15. Reference Design: Evaluation Board with 50 Matching Network Xo+ cE_ Eht + 5 cX gE_ A 8 cKs S T ,KcKh EJhJ i 3 EXs + _ cEt + 2Sg KQ_EBmtc_ 5S 5T KQ_EBm_ct 5i 53 KQ_EBcX KQ_EBocKs EXs EJhJ +zN Xto8zuz he+ he5 WoE KQ_EBocKs KQ_EBmtc_ KQ_EBcX Table 12. Frequency Dependent Component Values ...
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... PCB Layout Top View Bottom View Rev. 1.2 Si4322 39 ...
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... Si4322 17. Pin Descriptions—Si4322 DCLK / FFIT / CFIL Table 14. Pin Descriptions Pin Name Type 1 SDI DI Data input of serial control interface 2 SCK DI Clock input of serial control interface 3 nSEL DI Chip select input of serial control interface (active low) 4 SDO DO Serial data output. Tristate with bus-hold cell if nSEL = H ...
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... Ordering Guide Part Ordering # Si4322-A1-FT Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. Temperature Package –40 to +85 °C 16-Pin TSSOP Rev. 1.2 Si4322 41 ...
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... Si4322 19. Package Outline: 16-Pin TSSOP Figure 15 illustrates the package details for the Si4322. Table 15 lists the values for the dimensions shown in the illustration. Table 15. Package Diagram Dimensions (mm) Dimension θ aaa bbb ccc 42 Figure 15. 16-Pin TSSOP Min Nom Max — — 1.20 0.05 — ...
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... N : OTES Rev. 1.2 Si4322 43 ...
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... Si4322 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: wireless@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...