SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 30

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

Si4322
8. Power Saving Modes
The different operating modes of the chip depend on the following control bits:
eb, et, ex bits—"5.3. Configuration Setting Command" on page 16
elfc bit—"5.10. Low Battery Detector and Microcontroller Clock Divider Command" on page 21
en bit—"5.5. Receiver Setting Command" on page 18
Active mode—The whole receiver chain and the crystal oscillator both turned on.
Idle mode—The receiver is not active, only the crystal oscillator is running.
Sleep mode—Only the low frequency (32 kHz) RC oscillator is running. This oscillator also runs when the wake-up
timer or the low battery detector is enabled, providing them a timing signal.
Stand-by mode—All circuits are turned off.
9. Dual Clock Output
When the chip is switched into idle mode, the 10 MHz crystal oscillator starts. After oscillation ramp-up a 1 MHz
clock signal is available on the CLK pin. This (fast) clock frequency can be reprogrammed during operation with the
"5.10. Low Battery Detector and Microcontroller Clock Divider Command" on page 21. During startup and in sleep
or standby mode (crystal oscillator disabled), the CLK output is pulled to logic low.
On the same pin a low frequency clock signal can be obtained if the elfc bit is set in the low battery and
microcontroller clock divider command. The clock frequency is 32 kHz, which is derived from the low-power RC
oscillator. The clock signal is present on the CLK pin regardless the state of the dc bit in the "5.3. Configuration
Setting Command" on page 16.
Driving the output will increase the sleep mode supply current. Actual worst-case value can be determined when
the exact load and min/max operating conditions are defined. After power-on reset the chip goes into sleep mode
and the slow frequency clock appears on the CLK pin.
Switching back into fast clock mode can be done by setting the ex bit in the configuration setting command or the
en bit in the "5.5. Receiver Setting Command" on page 18. It is important to leave bit dc in the Configuration Setting
Command at its default state (0) otherwise there will be no clock signal on the CLK pin.
Switching between the fast and slow clock modes is glitch-free in a sense that either state of the clock lasts for at
least a half cycle of the fast clock. During switching the clock can be logic low once for an intermediate period i.e.
for any time between the half cycle of the fast and the slow clock.
30
Slow clock feature can be enabled by entering into sleep mode (clearing the en and ex bits and setting the elfc bit).
*Note: Maximum value.
Operating
Standby
Mode
Active
Sleep
Idle
eb or et or
elfc
X
X
1
0
Rev. 1.2
en
1
0
0
0
ex
X
1
0
0
I
DD
0.5 mA
12 mA
0.3 µA
5 µA*
(typ)