ATA5811-PLHC Atmel, ATA5811-PLHC Datasheet - Page 26

• Manufacturer Part Number: ATA5811-PLHC
• Description: IC TXRX UHF ASK/FSK 1CH 48-QFN
• Manufacturer: Atmel

Specifications of ATA5811-PLHC

• Frequency: 433MHz, 868MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Access Control, AMR, RKE
• Power - Output: 5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.4 V ~ 3.6 V or 4.4 V ~ 6 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 16mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Other names: ATA5811-PLHCTR; ATA5811-PLQ; ATA5811-PLQTR; ATA5811-PLQTR

6.1
Figure 6-3.
6.2
26
Pin CLK
Basic Clock Cycle of the Digital Circuitry
ATA5811/ATA5812
(Control register 3)
Clock Timing
N_RESET
CLK_ON
VSOUT
CLK
The variable FREQ depends on FREQ2 and FREQ3, which are defined by the bits FR0 to FR8
in control register 2 and 3 and is calculated as follows:
FREQ = 3584 + FREQ2 + FREQ3
Only the range of FREQ = 3803 to 4053 of this register should be used because otherwise har-
monics of f
FREQ_max = 4053). The resulting tuning range is ±118 ppm at 868.3 MHz and more than
±150 ppm at 433.92 MHz or 315 MHz.
Pin CLK is an output to clock a connected microcontroller. The clock frequency f
as follows:
Because the enabling of pin CLK is asynchronous the first clock cycle may be incomplete. The
signal at CLK output has a nominal 50% duty cycle.
The complete timing of the digital circuitry is derived from one clock. According to
on page
a divider.
T
f
f
DCLK
DCLK
CLK
• Timing of the polling circuit including Bit-check
• TX bit rate
V
Thres_2
=
=
controls the following application relevant parameters:
f
---------- -
f
---------- -
XTO
25, this clock cycle T
= 2.38V (typically)
XTO
16
3
XTO
and f
V
Thres_2
CLK
= 2.38V (typically)
can cause interference with the received signals (FREQ_min = 3803,
DCLK
is derived from the crystal oscillator (XTO) in combination with
CLK
4689F–RKE–08/06
is calculated
Figure 6-2