ADF7020-1BCPZ Analog Devices Inc, ADF7020-1BCPZ Datasheet
ADF7020-1BCPZ
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ADF7020-1BCPZ Summary of contents
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... PFD DIV R RING OSC CPOUT OSC1 OSC2 Figure 1. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 High Performance FSK/ASK Transceiver IC ADF7020-1 MUXOUT TEST MUX FSK/ASK DATA SYNCHRONIZER CE AGC DATA CLK CONTROL Tx/Rx DATA I/O CONTROL AFC ...
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... Reference Input........................................................................... 15 Choosing Channels for Best System Performance................. 17 Transmitter ...................................................................................... 18 RF Output Stage.......................................................................... 18 Modulation Schemes.................................................................. 18 Receiver Section.............................................................................. 20 RF Front End............................................................................... 20 RSSI/AGC.................................................................................... 21 FSK Demodulators on the ADF7020-1 ................................... 21 FSK Correlator/Demodulator................................................... 21 Linear FSK Demodulator .......................................................... 23 AFC Section ................................................................................ 23 Automatic Sync Word Recognition ......................................... 24 Applications..................................................................................... 25 REVISION HISTORY 12/05—Revision 0: Initial Version LNA/PA Matching ...
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... The transmit section contains a VCO and low noise fractional-N PLL with output resolution of <1 ppm. This frequency agile PLL allows the ADF7020 used in frequency-hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. ...
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... ADF7020-1 SPECIFICATIONS 3.6 V, GND = All measurements are performed using the EVAL-ADF7020-1-DBX and PN9 data sequence, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) Frequency Ranges (Divide-by-2 Mode) VCO Frequency Range Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Data Rate ...
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... Rev Page ADF7020-1 Unit Test Conditions At BER = 1E − 3, FRF = 315 MHz, LNA and PA matched separately dBm FDEV= 5 kHz, high sensitivity mode dBm FDEV = 10 kHz, high sensitivity mode At BER = 1E − ...
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... ADF7020-1 Parameter PHASE-LOCKED LOOP VCO Gain Phase Noise (In-Band) Normalized In-Band Phase Noise 9 Floor Phase Noise (Out-of-Band) Residual FM PLL Settling REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time Input Level ADC PARAMETERS INL DNL TIMING INFORMATION Chip Enabled to Regulator Ready ...
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... This figure can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance as seen at the PA output: –198 + 10 log(f Min Typ Max 2.3 3.6 13/16/21 17.6 20.1 0 log N. PFD Rev Page ADF7020-1 Unit Test Conditions V All V pins must be tied together DD FRF = 315 MHz 3 matched Ω mA VCO_BIAS_SETTING = 2 mA VCO_BIAS_SETTING = 2 ...
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... ADF7020-1 TIMING CHARACTERISTICS ± 10%, VGND = 25°C, unless otherwise noted. Guaranteed by design, but not production tested Table 2. Parameter Limit MIN t < < < < < < < < <10 10 SCLK t 1 SDATA DB31 (MSB) SLE SCLK SDATA REG7 DB0 (CONTROL BIT C1) SLE t 3 SREAD t 8 Unit ...
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... DATA RATE/32 RxCLK RxDATA DATA TxCLK DATA TxDATA FETCH SAMPLE NOTES 1. TxCLK ONLY AVAILABLE IN GFSK MODE. 1/DATA RATE Figure 4. RxData/RxCLK Timing Diagram 1/DATA RATE Figure 5. TxData/TxCLK Timing Diagram Rev Page ADF7020-1 ...
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... ADF7020-1 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND DD Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MLF θ Thermal Impedance JA Reflow Soldering Peak Temperature Time at Peak Temperature 1 GND = CPGND = RFGND = DGND = AGND = 0 V ...
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... CE Chip Enable. Bringing CE low puts the ADF7020-1 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. 25 SLE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches ...
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... Mnemonic Description 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7020-1 to the microcontroller. The SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin. 28 SCLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge ...
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... MARKER 1.834000000GHz –62.57dB 1 AA START 800MHz STOP 5.000GHz #RES BW 30kHz VBW 30kHz SWEEP 5.627s (601pts) Figure 11. Harmonic Response, Murata Dielectric Filter ATTEN 30dB OOK ASK GOOK AA CENTER 415.000 0 MHz #RES BW 360 Hz VBW 360 Hz SWEEP 2.791 s (601pts) ADF7020-1 –62.57dB SPAN 300 kHz ...
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... ADF7020-1 20 9μA 15 11μ –5 –10 –15 –20 – SETTING Figure 13. PA Output Power vs. Setting CARRIER POWER 10.75dBm ATTEN 6.00dB REF –70.00dBc/Hz 10.00 dB/ 1kHz FREQUENCY OFFSET Figure 14. Wideband Interference Rejection. Wanted Signal (880 MHz above Sensitivity Point Interferer = FM Jammer (9.76 kbps, 10k Deviation) ...
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... PFD [Hz] = XTAL/R MUXOUT and Lock Detect The MUXOUT pin allows the user to access various digital points in the ADF7020-1. The state of MUXOUT is controlled by Bits R0_DB (29:31). Regulator Ready Regulator ready is the default setting on MUXOUT after the transceiver has been powered up. The power-up time of the regulator is typically 50 μ ...
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... ADIsimPLL can be used to design loop filters for the ADF7020-1. N Counter The feedback divider in the ADF7020-1 PLL consists of an 8-bit integer counter and a 15-bit Σ-Δ fractional-N divider. The integer counter is the standard pulse-swallow type common in PLLs. This sets the minimum integer divide value to 31. The ...
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... The amplitude of beat-note spurs can be significantly reduced by using the frequency doubler to avoid very small or very large values in the fractional register. By having a channel 1 MHz away from an integer frequency, a 100 kHz loop filter can reduce the level to <−45 dBc. MUX TO PA Rev Page ADF7020-1 ...
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... ADF7020-1 TRANSMITTER RF OUTPUT STAGE The PA of the ADF7020-1 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver dBm into a 50 Ω load at a maximum frequency of 650 MHz. The PA output current and, consequently, the output power are programmable over a wide range. The PA configurations in FSK/GFSK and ASK/OOK modulation modes are shown in Figure 26 and Figure 27, respectively ...
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... VCO in OOK mode can lead to a wider than desired BW, especially not possible to increase the loop-filter BW > 300 kHz. The GOOK sampling clock samples data at the data INDEX _ COUNTER rate. (See the Setting Up the ADF7020-1 for GFSK section.) data sheet. Rev Page ADF7020-1 ...
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... ADF7020-1 RECEIVER SECTION RF FRONT END The ADF7020-1 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from power-line- induced interference problems. Figure 29 shows the structure of the receiver front end. The ...
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... additional factor should be introduced to account for losses in the front-end matching network/antenna. FSK DEMODULATORS ON THE ADF7020-1 The two FSK demodulators on the ADF7020-1 are • FSK correlator/demodulator • Linear demodulator Select these using the demodulator select bits, R4_DB (4:5). FSK CORRELATOR/DEMODULATOR The quadrature outputs of the IF filter are first limited and then ...
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... ADF7020-1 FREQUENCY CORRELATOR IF I LIMITERS Q IF – DEV DEV DB(4:13) DB(14) Figure 31. FSK Correlator/Demodulator Block Diagram Postdemodulator Filter A second-order digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user’s data rate. If the bandwidth is set too narrow, performance is degraded due to intersymbol interference (ISI) ...
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... In FSK mode, the output of the envelope detector provides an estimate of the average IF frequency. Two methods of AFC, external and internal, are supported on the ADF7020-1 (in FSK mode only). External AFC The user reads back the frequency information through the ADF7020-1 serial port and applies a frequency correction value to the fractional-N synthesizer’ ...
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... MHz 1.0 kbps ±5 kHz preprogrammed word is compared to the received bit stream, and the external pin INT/LOCK is asserted by the ADF7020-1 when a valid match is identified. This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational require- ments of the microprocessor and reduces the overall power consumption ...
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... Rx path, or alternatively by selecting one of the high linearity modes outlined in Table 6. Internal Rx/Tx Switch Figure 34 shows the ADF7020 configuration where the internal Rx/Tx switch is used with a combined LNA/PA matching network. This is the configuration used in the ADF7020-1DBX Evaluation boards. For most applications, the ...
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... DEVICE PROGRAMMING AFTER INITIAL POWER-UP Table 12 lists the minimum number of writes needed to set up the ADF7020-1 in either mode after CE is brought high. Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling AFC. When going from vice versa, the user needs to write only to the N register to alter the LO by 200 kHz and to toggle the Tx/Rx bit ...
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... Number of bits in payload by the bit period. AFC T 10 WR3 WR4 WR6 AGC/ CDR VCO RSSI Figure 38. Rx Programming Sequence and Timing Diagram Rev Page ADF7020-1 TIME Rx DATA OFF Signal to Monitor CLKOUT pin MUXOUT pin CVCO pin Analog RSSI on TEST_A pin (available by writing 0x3800 000C) ...
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... ADF7020-1 15mA TO 30mA 14mA 3.65mA 2.0mA REG. WR0 WR1 XTAL + VCO READY WR2 TxDATA Figure 39. Tx Programming Sequence and Timing Diagram Rev Page TIME T OFF ...
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... Bits RV5 to RV16. The revision code (RV) is coded with one quartet extending from Bits RV1 to RV4. The product code for the ADF7020-1 should read back 0x200. The current revision code should read back 0x6. 15 ...
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... ADF7020-1 REGISTER 0—N REGISTER MUXOUT 8-BIT INTEGER-N TRANSMIT/ TR1 RECEIVE 0 TRANSMIT 1 RECEIVE PLE1 PLL ENABLE 0 PLL OFF 1 PLL MUXOUT REGULATOR READY (DEFAULT DIVIDER OUTPUT DIGITAL LOCK DETECT ANALOG LOCK DETECT THREE-STATE PLL TEST MODES Σ-Δ TEST MODES Notes 1. The Tx/Rx bit (R0_DB27) configures the part mode and also controls the state of the internal Tx/Rx switch. ...
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... DIV-BY-2 0 DIRECT OUTPUT 1 DIVIDE-BY-2 VCO BIAS OUTPUT VB2 VB1 CURRENT 0 1 0.375mA 1 0 0.625mA . . 1 1 3.875mA I (MA) CP CP1 CP2 RSET 3.6kΩ 2.1 Figure 42. Rev Page ADF7020-1 ADDRESS R COUNTER BITS RF R COUNTER DIVIDE RATIO XTAL D1 DOUBLER 0 DISABLE ENABLED 1 CLK OUT ...
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... ADF7020-1 REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE) GFSK MOD PA BIAS CONTROL IC2 IC1 MC3 MC2 MC1 DI1 0 TxDATA 1 TxDATA PA2 PA1 PA BIAS 0 0 5μ 7μ 9μ 11μA Notes 1. Figure 13 shows how the PA bias affects the power amplifier level. The default level is 9 μA. If you need maximum power, program this value to 11 μ ...
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... PLL MODE 0 .... × F STEP 0 .... × F STEP 0 .... × F STEP . .... . . . . 1 .... 511 × F STEP Figure 44. Rev Page ADF7020-1 MODULATION ADDRESS SCHEME BITS PE1 POWER AMPLIFIER 0 OFF 1 ON MUTE PA UNTIL LOCK DETECT HIGH MP1 0 OFF MODULATION SCHEME FSK GFSK ASK OOK GOOK POWER AMPLIFIER OUTPUT LEVEL P6 ...
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... ADF7020-1 REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE) GFSK MOD PA BIAS CONTROL DI1 0 TxDATA 1 TxDATA PA2 PA1 PA BIAS 5μA 7μ 9μ 11μ IC2 IC1 INDEX_COUNTER 128 MC3 MC2 MC1 GFSK_MOD_CONTROL Notes GFSK_MOD_CONTROL 1. GFSK_DEVIATION = (2 2. Data rate = PFD/(INDEX_COUNTER × DIVIDER_FACTOR bias default = 9 μA. ...
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... The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to 40 kHz for ASK: XTAL = . SEQ _ CLK SEQ _ CLK _ DIVIDE CDR CLOCK DIVIDE SK3 SK2 SK1 SEQ_CLK_DIVIDE 254 255 FS8 FS7 ... FS3 FS2 FS1 0 0 ... ... ... . . . 1 1 ... ... Figure 46 Rev Page ADF7020-1 ADDRESS BITS BK2 BK1 BBOS_CLK_DIVIDE OK2 OK1 DEMOD_CLK_DIVIDE CDR_CLK_DIVIDE 254 255 ...
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... Notes 1. Demodulator Modes and 5 are modes that can be activated to allow the ADF7020-1 to demodulate data-encoding schemes that have run-length constraints greater than Post_Demod_BW = 2 π F /DEMOD_CLK, where the cutoff frequency (F CUTOFF be 0.75 times the data rate. 3. For Mode 5, the timeout delay to lock threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the Register 3— ...
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... The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware. 4. Choose a sync byte pattern that has good autocorrelation properties, for example, an unequal amount of digital 1s and 0s. SYNC BYTE SEQUENCE Figure 48. Rev Page ADF7020-1 CONTROL BITS SYNC BYTE PL2 PL1 LENGTH ...
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... ADF7020-1 REGISTER 6—CORRELATOR/DEMODULATOR REGISTER Rx RESET IF FILTER DIVIDER CA1 DEMOD 0 RESET 1 CDR ML1 MIXER LINEARITY RESET 0 DEFAULT 1 HIGH RxDATA INVERT RI1 RxDATA 0 RxDATA 1 FC9 . FC6 FC5 FC4 Notes 1. See the FSK Correlator/Demodulator section for an example of how to determine register settings. 2. Nonadherence to correlator programming guidelines results in poorer sensitivity. ...
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... AD1 AD2 AD1 ADC MODE 0 0 MEASURE RSSI 0 1 BATTERY VOLTAGE 1 0 TEMP SENSOR EXTERNAL PIN RB2 RB1 READBACK MODE 0 0 AFC WORD 0 1 ADC OUTPUT 1 0 FILTER CAL 1 1 SILICON REV Figure 50. Rev Page ADF7020-1 BITS DB1 DB0 C2(1) C1(1) ...
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... ADF7020-1 REGISTER 8—POWER-DOWN TEST REGISTER DB15 DB14 DB13 DB12 PD7 SW1 PD7 PA (Rx MODE OFF SW1 Tx/Rx SWITCH 0 DEFAULT (ON) 1 OFF LR2 LR1 RSSI MODE X 0 RSSI OFF X 1 RSSI ON PD6 0 1 Notes 1. For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition. ...
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... GAIN GAIN AGC HIGH THRESHOLD GS1 AGC SEARCH 0 AUTO AGC 1 HOLD SETTING GC1 GAIN CONTROL 0 AUTO 1 USER GH7 GH6 LG2 LG1 LNA GAIN < Figure 52. Rev Page ADF7020-1 ADDRESS AGC LOW THRESHOLD AGC LOW GL7 GL6 GL5 GL4 GL3 GL2 GL1 THRESHOLD ...
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... ADF7020-1 REGISTER 10—AGC 2 REGISTER I/Q PHASE ADJUST SIQ2 SELECT IQ 0 PHASE TO I CHANNEL 1 PHASE TO Q CHANNEL Notes 1. This register is not used under normal operating conditions. REGISTER 11—AFC REGISTER Notes 1. See the Internal AFC section to program AFC scaling coefficient bits. 2. The AFC scaling coefficient bits can be programmed using the following formula: AFC_Scaling_Coefficient = Round((500 × ...
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... CAL SOURCE 0 INTERNAL 1 SERIAL IF BW CAL Using the Test DAC on the ADF7020-1 to Implement Analog FM Demodulation and Measuring of SNR The test DAC allows the output of the postdemodulator filter for both the linear and correlator/demodulators (Figure 31 and Figure 32 viewed externally. It takes the 16-bit filter output and converts high frequency, single-bit output using a second-order error feedback Σ ...
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... ADF7020-1 REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER TEST DAC GAIN TEST DAC OFFSET REMOVAL Notes 1. Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low signal maximum of a 300 kHz offset can be removed and gained to use the full dynamic range of the DAC: ...
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... MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADF7020-1BCPZ −40°C to +85°C 1 ADF7020-1BCPZ-RL −40°C to +85°C 1 ADF7020-1BCPZ-RL7 −40°C to +85°C EVAL-ADF70XXMB EVAL-ADF70XXMB2 EVAL-ADF7020-1DB4 EVAL-ADF7020-1DB5 Pb-free part. 7.00 BSC SQ 0.60 MAX 37 36 TOP 6.75 VIEW BSC SQ 0 ...
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... ADF7020-1 NOTES Rev Page ...
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... NOTES Rev Page ADF7020-1 ...
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... ADF7020-1 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05669–0–12/05(0) Rev Page ...