ADF7020-1BCPZ Analog Devices Inc, ADF7020-1BCPZ Datasheet - Page 12

• Manufacturer Part Number: ADF7020-1BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020-1BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 17.6mA
• Current - Transmitting: 21mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Receiving Current: 20.1mA
• Transmitting Current: 13mA
• Data Rate: 200Kbps
• Frequency Range: 135MHz To 650MHz
• Modulation Type: ASK, FSK, GFSK, GOOK, OOK
• Rf Ic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020-1DBZ8 - BOARD EVAL ADF7020-1 128-142MHZEVAL-ADF7020-1DBZ7 - BOARD EVAL ADF7020-1 310-340MHZEVAL-ADF7020-1DBZ6 - BOARD EVAL ADF7020-1 470-510MHZEVAL-ADF7020-1DBZ4 - BOARD EVAL ADF7020-1 405-435MHZEVAL-ADF7020-1DBZ5 - BOARD EVAL ADF7020-2 ADJ FREQ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ADF7020-1
Pin No.
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44, 46
45, 47
48
Mnemonic
SREAD
SCLK
GND2
ADCIN
CREG2
VDD2
INT/LOCK
DATA I/O
DATA CLK
CLKOUT
MUXOUT
OSC2
OSC1
VDD3
CREG3
CPOUT
VDD
L2, L1
GND, GND1
CVCO
Description
Serial Data Output. This pin is used to feed readback data from the ADF7020-1 to the microcontroller. The SCLK
input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
Ground for Digital Section.
Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 to 1.9 V.
Readback is made using the SREAD pin.
Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this
pin and ground for regulator stability and noise rejection.
Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin.
Bidirectional Pin. In output mode (interrupt mode), the ADF7020-1 asserts the INT/LOCK pin when it has found
a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the
demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can
be reliably received. In this mode, a demodulator lock can be asserted with minimum delay.
Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply.
Transmit/Receive Clock Pin. In receive mode, the pin outputs the synchronized data clock. The positive clock
edge is matched to the center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to
latch the data from the microcontroller into the transmit section at the exact required data rate. See the
Gaussian Frequency Shift Keying (GFSK) section.
A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to
drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio.
Multiplexer Output Pin. This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked
to the correct frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial
interface regulator.
Oscillator Output Pin. The reference crystal should be connected between this pin and OSC1. A TCXO reference
can be used by driving this pin with CMOS levels and disabling the crystal oscillator.
Oscillator Input Pin. The reference crystal should be connected between this pin and OSC2.
Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 μF
capacitor.
Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be
placed between this pin and ground for regulator stability and noise rejection.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated
current changes the control voltage on the input to the VCO.
Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 μF capacitor.
External VCO Inductor Pins. A chip inductor should be connected across these pins to set the VCO operating
frequency. See the Voltage Controlled Oscillator (VCO) section for details on choosing the appropriate value.
Grounds for VCO Block.
VCO Noise Compensation Node. A 22 nF capacitor should be placed between this pin and CREG1 to reduce
VCO noise.
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