ADF7020-1BCPZ Analog Devices Inc, ADF7020-1BCPZ Datasheet - Page 8

• Manufacturer Part Number: ADF7020-1BCPZ
• Description: IC TX FSK/ASK ISM BAND 48LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADF7020-1BCPZ

• Design Resources: Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Frequency: 431MHz ~ 478MHz and 862MHz ~ 956MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Power - Output: -16dBm ~ 13dBm
• Sensitivity: -119dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 17.6mA
• Current - Transmitting: 21mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LFCSP
• Receiving Current: 20.1mA
• Transmitting Current: 13mA
• Data Rate: 200Kbps
• Frequency Range: 135MHz To 650MHz
• Modulation Type: ASK, FSK, GFSK, GOOK, OOK
• Rf Ic Case Style: LFCSP
• No. Of Pins: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF7020-1DBZ8 - BOARD EVAL ADF7020-1 128-142MHZEVAL-ADF7020-1DBZ7 - BOARD EVAL ADF7020-1 310-340MHZEVAL-ADF7020-1DBZ6 - BOARD EVAL ADF7020-1 470-510MHZEVAL-ADF7020-1DBZ4 - BOARD EVAL ADF7020-1 405-435MHZEVAL-ADF7020-1DBZ5 - BOARD EVAL ADF7020-2 ADJ FREQ
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ADF7020-1
TIMING CHARACTERISTICS
V
Table 2.
Parameter
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
8
9
10
DD
= 3 V ± 10%, VGND = 0 V, T
SREAD
SDATA
SDATA
SCLK
SCLK
SLE
SLE
(CONTROL BIT C1)
DB31 (MSB)
t
1
REG7 DB0
Limit at T
<10
<10
<25
<25
<10
<20
<25
<25
<10
t
3
MIN
t
A
2
= 25°C, unless otherwise noted. Guaranteed by design, but not production tested.
to T
t
t
1
8
MAX
DB30
X
t
2
t
9
Figure 2. Serial Interface Timing Diagram
Figure 3. Readback Timing Diagram
RV16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 8 of 48
DB2
t
3
RV15
Test Conditions/Comments
SDATA-to-SCLK set-up time
SDATA-to-SCLK hold time
SCLK low duration
SLE pulse width
SCLK high duration
SCLK-to-SLE set-up time
SCLK-to-SREAD data valid, readback
SREAD hold time after SCLK, readback
SCLK-to-SLE disable time, readback
t
4
(CONTROL BIT C2)
DB1
RV2
(CONTROL BIT C1)
t
5
DB0 (LSB)
t
10
RV1
t
6