CYRF69103-40LFXC Cypress Semiconductor Corp, CYRF69103-40LFXC Datasheet - Page 27

• Manufacturer Part Number: CYRF69103-40LFXC
• Description: IC PROC 8K FLASH 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CYRFr

Specifications of CYRF69103-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: ISM
• Applications: General Purpose
• Power - Output: 6dBm
• Sensitivity: -87dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 21.9mA
• Current - Transmitting: 39.9mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Processor Series: CYRF691x
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Height: 1 mm
• Length: 5.9 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Width: 5.9 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1933

Table 15-3. OSC Control 0 (OSC_CR0) [0x1E0] [R/W]
Document #: 001-07611 Rev *F
Bits 7:6
Bit 5
Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the following Sleep [1:0] bits.
Bits 4:3
Note Sleep intervals are approximate
Bits 2:0
Sleep Timer
Bit #
Field
Read/Write
Default
CPU Speed
[1:0]
00
01
10
11
[2:0]
000
001
010
100
101
011
110
111
Reserved
No Buzz
During sleep (the Sleep bit is set in the CPU_SCR
circuit is turned on periodically to detect any POR and LVD events on the V
ECO_TR are used to control the duty
events, the No Buzz bit is used to force the LVD and POR detection circuit to be continuously enabled during
sleep. This results in a faster response to an LVD or POR event during sleep at the expense of a slightly higher
than average sleep current. Obtaining the absolute lowest power usage in sleep mode requires the No Buzz bit be
clear
0 = The LVD and POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle.
1 = The Sleep Duty Cycle value is overridden. The LVD and POR detection circuit is always enabled.
CPU Speed [2:0]
The CYRF69103 may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero.
Therefore, the default CPU speed is 3 MHz
Sleep Timer [1:0]
Frequency (Nominal)
Sleep Timer Clock
Oscillator is selected
7
–
0
CPU when Internal
3 MHz (Default)
512 Hz
Reserved
64 Hz
8 Hz
1 Hz
Reserved
Reserved
1.5 MHz
750 kHz
187 kHz
12 MHz
6 MHz
6
–
0
Sleep Period
(Nominal)
1.95 ms
15.6 ms
125 ms
1 sec
No Buzz
R/W
5
0
cycle—Table 18-3
.
Watchdog Period
(Nominal)
R/W
375 ms
4
Sleep Timer [1:0]
0
47 ms
Register—Table 16-1
3 sec
6 ms
on page 36). To facilitate the detection of POR and LVD
R/W
3
1
on page 31), the LVD and POR detection
CC
R/W
pin (the Sleep Duty Cycle bits in the
2
0
CPU Speed [2:0]
R/W
1
0
CYRF69103
Page 27 of 68
R/W
0
0
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