MRF49XAT-I/ST Microchip Technology, MRF49XAT-I/ST Datasheet
MRF49XAT-I/ST
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... Microchip Technology Inc. MRF49XA Data Sheet ISM Band Sub-GHz RF Transceiver Preliminary DS70590B ...
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... PICDEM, PICDEM.net, PICtail, PIC Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... High-Resolution Programmable PLL Synthesizer • Integrated Power Amplifier • Integrated Low Phase Noise VCO Frequency • Synthesizer and PLL Loop Filter • Automatic Frequency Control © 2009 Microchip Technology Inc. MRF49XA Baseband Features • Supports Programmable TX Frequency Deviation and RX Baseband Bandwidth • ...
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... MRF49XA Pin Diagram: 16-Pin TSSOP FSK/DATA/FSEL RCLKOUT/FCAP/FINT CLKOUT DS70590B-page 2 SDI 1 16 SCK SDO 13 4 MRF49XA IRQ Preliminary INT/DIO RSSIO V DD RFN RFP V SS RESET RFXTL/EXTREF © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. Preliminary MRF49XA DS70590B-page 3 ...
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... MRF49XA NOTES: DS70590B-page 4 Preliminary © 2009 Microchip Technology Inc. ...
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... INTRODUCTION Microchip Technology’s MRF49XA is a fully integrated Sub-GHz RF transceiver. This low-power single chip FSK baseband transceiver supports: • Zero-IF architecture • Multi-channel and multi-band • Synthesizer with Phase Locked Loop (PLL) • Power Amplifier (PA) • Low Noise Amplifier (LNA) • ...
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... Unit Block Power Memory Management 10 MHz MCU MRF49XA INT IRO __ CS I/O/SS SDO SDI SDO SDI SCK SCK I/O INT/DIO* I/O RESET* I/O FSK/DATA/FSEL* CLKOUT* OSC1 I/O RCLKOUT/FCAP/FINT* Preliminary SPI Signals MCU Interface Other Handshaking Signals © 2009 Microchip Technology Inc. ...
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... The device operates in the low-voltage range of 2.2V to 3.8V, and in Sleep mode, it operates at a very low-current state, typically 0.3 μA. © 2009 Microchip Technology Inc. The quality of the data is checked or validated using the RSSI and DQI blocks built into the transceiver. Data is buffered in transmitter registers and receiver FIFOs ...
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FIGURE 2-1: MRF49XA ARCHITECTURAL BLOCK DIAGRAM MIX I LNA RFN 13 RFP 12 MIX Q PA PLL and I/Q VCO with Calibration PA/LNA and PLL/CLK Block WUTM CLK OSC with calibration Clock Block 8 9 RFXTL/ CLKOUT EXTREF Cal AMP ...
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... Digital Input/Output Recovery Clock Output: Provides the clock recovered from FINT 8 CLKOUT Digital Output © 2009 Microchip Technology Inc. Type Serial data input interface to MRF49XA (SPI input signal). Serial clock interface (SPI clock). Serial interface chip select (SPI chip/device select). Serial data output interface from MRF49XA (SPI output signal) ...
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... STSREG (see Table 2-4). This pin can be used to wake-up the device from Sleep. Data Indicator Output: This pin can be configured to indicate valid data based on the actual internal settings. Preliminary Description © 2009 Microchip Technology Inc. ...
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... POR. The RESET pin has an internal, weak, on-chip, pull-up resistor. The device will not accept commands during the Reset period. © 2009 Microchip Technology Inc. The device enters the Reset mode if any of the following events take place: • Power-on Reset • ...
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... In Fast mode, it uses less samples ( bits) before locking, and thereby, the settling time is short which makes timing accuracy less critical. The RCLKOUT/FCAP/FINT recovered from the incoming data if the baseband filter is configured as a digital filter. Preliminary © 2009 Microchip Technology Inc. pin provides the clock ...
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... RF input power is graphically represented in Figure 2-2. FIGURE 2-2: ANALOG RSSI VOLTAGE 1150 450 • © 2009 Microchip Technology Inc. 2.10.2 DATA QUALITY INDICATOR The Data Quality Indicator (DQI special function which indicates the quality of the received signal and the link. The unfiltered received data is sampled and the number of spikes are counted in the received data for a specified time ...
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... TX register is enabled to take care of the transmission. • As DATA (Data Out), this pin receives the data in conjunction with RCLKOUT when the internal FIFO is not used. When reading the internal RXFIFOREG, this pin must be pulled “low”. Preliminary © 2009 Microchip Technology Inc. ...
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... SDI pin are shifted into the device on the rising edge of the clock on the SCK pin.The serial interface is initialized if the CS signal is high. © 2009 Microchip Technology Inc. 2.15 Serial Peripheral Interface The MRF49XA communicates with the host micro- controller via a 4-wire SPI port as a slave device ...
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... Wake-up timer values for time interval Duty Cycle mode and value Low battery detect threshold values and clock output frequency Clock out buffer speed, PLL bandwidth, dithering and delay Preliminary Related Control Functions © 2009 Microchip Technology Inc. ...
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TABLE 2-5: CONTROL (COMMAND) REGISTER MAP Reg. Name Bit 15 Bit 14 Bit 13 Bit 12 STSREG TXRXFIFO POR TXOWRXOF WUTINT LCEXINT GENCREG AFCCREG TXCREG TXBREG 1 0 ...
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... This bit is cleared after STSREG is read. 5: DS70590B-page 18 R-0 R-0 WUTINT LCEXINT R-0 R-0 OFFSV U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2,3) (5) (5) (5) (5) Preliminary (1) R-0 R-0 R-0 LBTD FIFOEM ATRSSI bit 8 R-0 R-0 R-0 OFFSB<3:0> bit Bit is unknown (5) © 2009 Microchip Technology Inc. ...
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... The actual frequency offset can be calculated as the AFC offset value multiplied by the current PLL frequency step from CFSREG (FREQB<11:0>). This bit is cleared after STSREG is read. 5: See Appendix A: “Read Sequence and Packet Structures” for the STSREG read sequence,. Note: © 2009 Microchip Technology Inc. (1) (CONTINUED) Preliminary MRF49XA (4) ...
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... If the data FIFO is used, the DATA/FSK/FSEL pin must be pulled “low”. 2: DS70590B-page 20 R/W-0 R/W-0 CCB<15:8> R/W-0 R/W-1 FBS<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 LCS<3:0> bit Bit is unknown (2) © 2009 Microchip Technology Inc. ...
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... PLL. Reset this bit before initiating another sample. In High-Accuracy (Fine) mode, the processing time is twice the regular mode, but the uncertainty of the 3: measurement is significantly reduced. © 2009 Microchip Technology Inc. R/W-0 R/W-0 CCB<15:8> R/W-1 R/W-0 ARFO< ...
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... PLL. Reset this bit before initiating another sample. In High-Accuracy (Fine) mode, the processing time is twice the regular mode, but the uncertainty of the 3: measurement is significantly reduced. DS70590B-page 22 for each band is as follows: RES Preliminary © 2009 Microchip Technology Inc. ...
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... The transmitter FSK modulation parameters are used for calculating the resulting output frequency, as Note 1: shown in Equation 2-1. The output transmit power range is relative to the maximum available power, which depends on the actual 2: antenna impedance. © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-0 CCB<15:9> R/W-0 ...
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... The output transmit power range is relative to the maximum available power, which depends on the actual 2: antenna impedance. EQUATION 2- (– 1)SIGN x ( (15 kHz) FSKOUT 0 where the Channel Center Frequency (see Register 2-6 for the 4-Bit Binary Number (MODBW<3:0>) SIGN = MODPLY FSK XOR DS70590B-page 24 (2) Calculation) 0 Preliminary © 2009 Microchip Technology Inc. ...
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... TXDB<7:0>: Transmit Data Byte bits The transmit data bits hold the 8 bits that are to be transmitted. To use this register, set the bit, TXDEN = 1 (GENCREG<7>). If TXDEN is not set, use the FSK/DATA/FSEL pin to manually modulate the data. © 2009 Microchip Technology Inc. R/W-1 R/W-1 R/W-0 CCB< ...
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... Bit is cleared (1) . < 3903 VAL FA1 Min. (MHz) Max. (MHz) 430.2400 439.7575 860.4800 879.5150 900.7200 929.2725 Preliminary R/W-1 R/W-1 R/W-0 FREQB<11:8> bit 8 R/W-0 R/W-0 R/W-0 bit Bit is unknown ) must VAL FA0 Tuning Resolution (kHz) 2.5 5.0 7.5 © 2009 Microchip Technology Inc. ...
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... RXLNA<1:0>: Receiver LNA Gain bits These bits, when set to different values, can accommodate environments with high interferences. The LNA gain also affects the true RSSI value - - © 2009 Microchip Technology Inc. R/W-1 R/W-0 R/W-0 FINTDIO R/W-0 R/W-0 R/W-0 RXLNA<1:0> ...
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... These bits can be set to indicate the incoming signal strength above a preset limit. The result enables or disables the DQDO bit (STSREG<7>). 111 = Reserved 110 = Reserved 101 = -73 dB 100 = -79 dB 011 = -85 dB 010 = -91 dB 001 = -97 dB 000 = -103 dB DS70590B-page 28 Preliminary © 2009 Microchip Technology Inc. ...
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... The DQI parameter is calculated using Equation 2-3. The DQI parameter in BBFCREG should be chosen 2: according to the following rules: - The parameter should be > 4, otherwise, noise might be treated as a valid FSK signal. - The maximum value is 7. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 CCB<15:8> ...
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... CAPACITOR VALUE Data Rate 1.2 kbps 2.4 kbps 4.8 kbps 9.6 kbps 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps 256 kbps Preliminary © 2009 Microchip Technology Inc. . FILTER VS Filter Capacitor Value 12 nF 8.2 nF 6.8 nF 3.3 nF 1.5 nF 680 pF 270 pF 150 pF 100 pF ...
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... RXDB<7:0>: Receiver Data Byte bits These are the recovered data bits stored in the FIFO. The controller can read 8 bits from the receiver FIFO over the SPI bus. The FIFOEN bit (GENCREG<6>) should be set to receive these bits. © 2009 Microchip Technology Inc. R/W-1 R/W-0 R/W-0 CCB< ...
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... For Reset mode selection, see Table 2-10. 3: DS70590B-page 32 R/W-0 R/W-1 R/W-0 CCB<15:8> R/W-0 R/W-0 R/W-0 SYCHLEN FFSC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-1 R/W-0 bit 8 R/W-0 R/W-0 FSCF DRSTM bit Bit is unknown (2) © 2009 Microchip Technology Inc. ...
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... RESET MODE SELECTION DRSTM Reset Mode Normal Reset 1 Sensitive Reset 0 See Appendix A: “Read Sequence and Packet Structures” for FIFO packet structures. Note: © 2009 Microchip Technology Inc. SCL1 SCL0 NA 0xD4 0x2D 0xD4 Reset is triggered when V Reset is triggered when V is greater than 600 mV ...
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... The SYNBREG assigns the value to SCL0 of the synchronous character in the FIFORSTREG. The value is valid for a byte or word long synchronous character. DS70590B-page 34 R/W-0 R/W-1 R/W-1 CCB<15:8> R/W-1 R/W-0 R/W-1 SYNCB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Fast Mode Accuracy (FMA) = ΔDR/DR < 3/(29 x LN) where the longest number of expected ones or zeros in the data stream. ΔDR is the difference in the actual data rate versus the set data rate in the transmitter the expected data rate set using DRPV<6:0>. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-1 CCB<15:8> ...
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... OSCEN bit is cleared. The device will not fully enter into the Sleep mode. DS70590B-page 36 R/W-0 R/W-0 R/W-0 CCB<15:8> R/W-0 R/W-1 R/W-0 SYNEN OSCEN LBDEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (3) Preliminary R/W-1 R/W-0 bit 8 R/W-0 R/W-0 (3) WUTEN CLKOEN bit Bit is unknown (2) © 2009 Microchip Technology Inc. ...
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... See WTSREG (Register 2-14) for details on programming the wake-up timer value the CLKOEN bit is cleared by enabling the clock output, the oscillator continues to run even if the 4: OSCEN bit is cleared. The device will not fully enter into the Sleep mode. © 2009 Microchip Technology Inc. (2) (4) Preliminary MRF49XA ...
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... WTMV<7:0> = Decimal Value between 0 to 255 WTEV<4:0> = Decimal Value between DS70590B-page 38 R/W-0 R/W-0 R/W-0 WTEV<4:0> R/W-1 R/W-0 R/W-1 WTMV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) WTEV<4:0> + 0.5 ms Preliminary R/W-0 R/W-1 bit 8 R/W-1 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Sleep. The process in the Duty Cycle mode starts over. The duty cycle uses the multiplier value of the wake-up timer, in parts for its calculation, as shown in Equation 2-8. EQUATION 2- (DCMV<7:1> 1)/WTMV<7:0> x 100% where: WTMV is WTMV<7:0> bits of the WTSREG. © 2009 Microchip Technology Inc. R/W-0 R/W-1 R/W-0 CCB<15:8> R/W-0 ...
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... Threshold Voltage Value = 2.25 + 0.1 x (LBDVB<3:0>) where: LBDVB<3:0> is the Decimal Value from 0 to 15. DS70590B-page 40 R/W-0 R/W-0 R/W-0 CCB<15:8> R/W-0 R/W-0 R/W-0 r LBDVB<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1,2) © 2009 Microchip Technology Inc. ...
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... Enabling the bit configures higher data rates, faster settling and reduced phase noise; thus, resulting in a better RF performance -102 dBc/Hz, > 90 kbps (max 256 kbps -107 dBc/Hz, < 90 kbps (max 86.2 kbps) © 2009 Microchip Technology Inc. R/W-0 R/W-1 R/W-1 CCB<15:8> ...
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... MRF49XA NOTES: DS70590B-page 42 Preliminary © 2009 Microchip Technology Inc. ...
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... FIGURE 3-1: POWER-ON RESET EXAMPLE V DD 1.6V H RESET Output L (Pin 10) © 2009 Microchip Technology Inc. 3.1 Reset The MRF49XA supports four types of Reset: • Power-on Reset • Power Glitch Reset • Software Reset • Reset Pin 3.1.1 POWER-ON RESET The MRF49XA has a built-in Power-on Reset circuitry which automatically resets all control registers when power is applied ...
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... The Reset event reinitializes the internal Note: registers, and thus, the Sensitive mode is enabled again. Reset Threshold Voltage (600 m V) Preliminary level reaches the Reset threshold requires 250 mV to trigger a DD Reset Ram p Line (100 m V/m s) Tim e © 2009 Microchip Technology Inc. ...
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... Reset (Input/Output*) RESET Pin These pins can be left floating. © 2009 Microchip Technology Inc. Reset Threshold Voltage (600 m V) The registers associated with Reset are: • STSREG (see Register 2-1) • FIFORSTREG (see Register 2-10) • WTSREG (see Register 2-14) 3.2 ...
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... The microcontroller clock source (if the clock is not sup- plied by the MRF49XA) should be stable enough over temperature and voltage ranges to ensure a minimum of 16 bits time delay under all operating circumstances. Preliminary © 2009 Microchip Technology Inc. Load CAP0 Capacitance 0 8.5 ...
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... When set, the SYNEN bit (PMCREG<4>) enables the synthesizer. © 2009 Microchip Technology Inc. The PLL circuit automatically performs the fine adjust- ment of carrier frequency. This way, the receiver can minimize the offset between a transmit and receive frequency ...
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... Deviation [± kHz Deviation [± kHz Deviation [± kHz Deviation [± kHz] 120 135 150 165 Preliminary ) is used as the reference of ref is directly proportional ref ) and m 105 120 100 100 105 120 100 100 105 120 180 195 © 2009 Microchip Technology Inc. . ...
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... In the actual application, when the user applies a battery, the circuit measures and compensates for the frequency offset © 2009 Microchip Technology Inc. caused by the crystal tolerances. This method allows the use of a low-cost quartz crystal in the application and provides protection against interference ...
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FIGURE 3-6: AFC CIRCUIT FOR FREQUENCY OFFSET CORRECTION Baseband Signal IN FINE HAM SEL MHz CLK /4 11 MUX Enable Calculation FIFOEN DIO Auto Operation AUTOMS<1:0> POR Range Limit ARFO<1:0> Strobe MFCS Output Enable FOREN FREQB<11:0> Parameter ...
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... CFSREG (see Register 2-6) • RXCREG (see Register 2-7) • FIFORSTREG (see Register 2-10) • DRSREG (see Register 2-12) • PMCREG (see Register 2-13) © 2009 Microchip Technology Inc. 3.9 Interrupts The advanced interrupt handler circuit is implemented in the MRF49XA to reduce the power consumption. As ...
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... FIFO is read (receive FIFO interrupt thresh- old number of bits have been read). The receiver is switched off or the RXFIFO is switched off. 3.9.2.2 POR The IRO pin and its status bit are cleared by reading the Status Read register. Preliminary goes below the DD © 2009 Microchip Technology Inc. ...
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... W UTINT W UTEN LCEXINT (INT) FINTDIO LBTD LBDEN © 2009 Microchip Technology Inc. state of the OSCEN bit in PMCREG. This way, the microcontroller can always have a clock signal to process the interrupt. To prevent high-current consumption, which results in short battery life highly recommended to process and clear interrupts before entering Sleep mode. The functions which are not necessary should be turned off to avoid unwanted interrupts ...
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... Figure 3-8 shows the full baseband amplifier transfer function This optimizes the chip area, cost and channel separation. 1.0E+03 1.0E+04 1.0E+05 Frequency (Hz) Example 3-1 shows the method to calculate the recom- mended frequency deviation and BBBW for the given specifications. Preliminary 1.0E+06 © 2009 Microchip Technology Inc. ...
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... DRSREG. The analog filtering does not use the FIFO and the clock. The clock is not provided for the demodulated data, and hence, there is no need for setting the correct bit rate. © 2009 Microchip Technology Inc deviation Amplitude Baseband Filter Characteristic ...
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... Figure 3-10 depicts the DIO logic block diagram. DQI DIORT0 SEL0 DIORT1 SEL1 FAST IN0 MEDIUM IN1 SLOW IN2 LOGIC HIGH IN3 SET Q RXCEN R/S FLIP/FLOP CLR Preliminary © 2009 Microchip Technology Inc. for valid data are MUX Y DIO CLR ...
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... The registers associated with the programmable synchronous byte are: • FIFORSTREG (see Register 2-10) • PMCREG (see Register 2-13) © 2009 Microchip Technology Inc. 3.13 Received Signal Strength Indicator The Received Signal Strength Indicator (RSSI) estimates the received signal power within the bandwidth of ISM channels ...
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... The registers associated with RSSI are: • STSREG (see Register 2-1) • GENCREG (see Register 2-2) • RXCREG (see Register 2-7) • PMCREG (see Register 2-13) Preliminary DRSSIT0 1.2 1 0.8 0.6 0.4 0.2 0 -52 -42 © 2009 Microchip Technology Inc. ...
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... Wake-up Timer: The WUTEN bit, when set, enables the wake-up timer. See Register 2-14 (WTSREG) for details on programming the wake-up timer interval. © 2009 Microchip Technology Inc. Clock Output: The CLKOEN bit, when set, disables the oscillator clock output. On device Reset or ...
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... Section 3.4 “Crystal Oscillator and Clock Output”. The registers associated with power management are: • STSREG (see Register 2-1) • GENCREG (see Register 2-2) • RXCREG (see Register 2-7) • PMCREG (see Register 2-13) Preliminary © 2009 Microchip Technology Inc. ...
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FIGURE 3-12: LOGIC CONNECTIONS BETWEEN POWER CONTROL BITS Enable Power Amplifier TXCEN Start TX Edge Detector Clear TX Latch (If TX latch is used) Enable RF SYNEN Synthesizer (Crystal Synthesizer must be ON) Enable RF Front RXCEN End Enable Baseband ...
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... GENCREG (see Register 2-2) • RCXREG (see Register 2-7) • BBFCREG (see Register 2-8) • PMCREG (see Register 2-13) • WTSREG (see Register 2-14) Start/Send Packet A B. Packet Packet A Packet B FIFO Read Preliminary Packet B. FIFO Read © 2009 Microchip Technology Inc. ...
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... Enable crystal or 3. Set the INT pin © 2009 Microchip Technology Inc. The device has the ability to wake itself up from Sleep mode through a wake-up timer. The WTSREG sets the wake-up interval for the MRF49XA. After setting the wake-up interval, the WUTEN bit (PMCREG<1>) should be cleared and set at the end of every wake-up cycle ...
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... Channel Center Frequency 0 (see Register 2-6 for the 4-bit Binary Number (MODBW<3:0>) SIGN = MODPLY SDI 8-Bit Shift Register (Default: AAh) CLK SDI 8-Bit Shift Register (Default: AAh) CLK Preliminary calculation) 0 FSK XOR TX_DATA SDO SDO © 2009 Microchip Technology Inc. ...
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... Bit Rate 11 MUX 1:8 Divider SEL Y 10 SCLK 11 MUX Serial Bus Data © 2009 Microchip Technology Inc. SDI SDO 8-Bit Shift Register CLK SDI SDO 8-Bit Shift Register CLK Note: The data registers’ content is initialized by clearing the TXCEN bit. Preliminary MRF49XA ...
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... GENCREG (see Register 2-2) • TXCREG (see Register 2-4) • TXBREG (see Register 2-5) • PMCREG (see Register 2-13) . OPERATION MODE VS Function Pin 6 TX data input FSEL input (TX Data register can be accessed) Preliminary Pin 7 Not used © 2009 Microchip Technology Inc. ...
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... SDO (Register interrupt in TX mode*) * The device is in Transmit (TX) mode when the RXCEN bit is cleared using the PMCREG. © 2009 Microchip Technology Inc. Do not switch the TXCEN off here, because the TX Byte 1 is not transmitted out only stored in the internal register ...
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... SDI pin are shifted into the device on the rising edge of the clock on the SCK pin. The serial interface is initialized every time if the CS signal is high. Figure 3-18 shows a simple receiver FIFO read over SPI lines Received Bits Out MSB Preliminary LSB © 2009 Microchip Technology Inc. ...
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... If the duty cycle of the clock signal is not 50%, the shorter period of the clock pulse should be at least 2/f © 2009 Microchip Technology Inc. 3.18.2 POLLING MODE When the FSEL signal is low, the FIFO output is con- nected directly to the SDO pin and its contents are clocked out by the SCK pin ...
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... FOFEN bit in AFCCREG. The registers associated with RX-TX alignment procedures are: • STSREG (see Register 2-1) • AFCCREG (see Register 2-3) • RXCREG (see Register 2-7) • PMCREG (see Register 2-13) Preliminary © 2009 Microchip Technology Inc. ...
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... tio tio 4.1 Antenna/Balun A balun circuit for a 50Ω antenna is shown in Figure 4-2. If low tolerance components (i.e., ±5%) are used with an appropriate ground, the impedance remains close to the 50Ω measurement. FIGURE 4-2: BALUN CIRCUIT RFP RFN © 2009 Microchip Technology Inc 2 ...
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... The four-layer PCB is shown in Figure 4-4. Signal/Power/RF and Dielectric Constant = 4.5 Signal/Power/RF and Signal Layout Dielectric Constant = 4.5 RF Ground Dielectric Constant = 4.5 Power Line Routing Dielectric Constant = 4.5 Ground Preliminary Inductance (nH) 62 15.4 13.6 Common Ground Common Ground © 2009 Microchip Technology Inc. ...
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... Self Resonant Frequency (SRF) should be at least two times higher than the operating frequency. © 2009 Microchip Technology Inc. • The additional trace length affects the crystal oscillator by adding parasitic capacitance to the overall load of the crystal. To minimize this, place the crystal as close as possible to the RF device. • ...
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... CLKOUT RFXTL/EXTREF TP1 CLK TP2 GND 10 MHz ___ RESET DS70590B-page 74 +3. 2.2 uF 0.01 uF 6.3V +3. Freq. C1 433 MHz 220 pF 868 MHz 47 pF 915 MHz 33 pF Preliminary 50Ω ANT 390 2 5.1 pF 100 2.7 pF 100 2.7 pF © 2009 Microchip Technology Inc. ...
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... SMT 0603, X7R 2.2 μF, 10V Capacitor, Tantalum, 10%, C3 SMT 3216-18 (A) U1 — MRF49XA Transceiver X1 10 MHz Crystal, ±10 ppm, 10 pF, SMT 5 x 3.2 mm © 2009 Microchip Technology Inc. Description Manufacturer Murata Murata Murata Murata Murata TDK Corporation MLG1608B33NJ TDK Corporation MLG1608B47NJ Murata ...
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... SMT 5 x 3.2 mm DS70590B-page 76 Description Manufacturer Murata Murata Murata Murata TDK Corporation MLG1608BR10J TDK Corporation MLG1608B8N2D TDK Corporation MLG1608B22NJ Murata Murata Kemet Microchip Abracon Preliminary Manufacturer PN GRM1885C1H330JA01D GRM1885C1H1R2CZ01D GRM1885C1H270JA01D GRM1885C1H2R7CZ01D GRM188R71H102KA01D GRM188R71H103KA01D T491A225K010AT MRF49XA-I/ST ABM3B-10.000MHZ-12-R80- B-1-U-T © 2009 Microchip Technology Inc. ...
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... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. SS (1) ...
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... Typ Max Unit — — 0 — — μA -1 — 1 μA -1 — 1 — — 0.4 V – 0.4 — — V — 3.75 V © 2009 Microchip Technology Inc. ...
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... AFC Locking Range : FSK deviation in the received fsk signal Typical Values 25°C, V Note 1: A BER = 10E – kHz, Δ kHz, Baud Rate = 1.2 kbps, digital filter with AFC disabled. 2: © 2009 Microchip Technology Inc. (1) Min (2) — (2) — (2) — 0 — — ...
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... Typ Max Unit 10 11 MHz μs 30 — μs 200 300 © 2009 Microchip Technology Inc. ...
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... PCB layout design. During the Power-on Reset period, commands are not accepted by the chip. In case of Software Reset (see 3: WTSREG (Register 2-14)), the Reset time-out is typically 0.25 ms. © 2009 Microchip Technology Inc. Condition Min — ...
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... Data Hold Time (SCK rising edge to SDI transition Data Delay Time OD FIGURE 5-1: SPI TIMING DIAGRAM SCK SDI BIT 15 BIT 14 BIT 13 SDO TXRXFIFO POR DS70590B-page 82 Parameter t CD BIT 8 BIT 7 BIT 1 DQDO OFFSB(0) TXOWRXOF ATRSSI Preliminary © 2009 Microchip Technology Inc. Minimum Value (ns SHI t SH BIT 0 FIFO OUT ...
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... LNA gain maximum, filter bandwidth 67 kHz, data rate 9.6 kbps, AFC switched off, FSK Note 1: deviation ± 45 kHz, V The ETSI limit given in the figure is drawn by taking -106 dBm at 9.6 kbps typical sensitivity 2: into account and corresponds to receiver class 2 requirements. © 2009 Microchip Technology Inc. (1, ...
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... Input Power (dBm) BER Curves in 868 MHz Band -105 -100 -95 -90 Input Power (dBm) Preliminary 1.0E+00 1.0E-01 1.0E-02 1.2k 9.6k 1.0E-03 19.2k 115.2k 1.0E-04 1.0E-05 1.0E-06 -90 1.0E+00 1.0E-01 1.0E-02 1.2k 9.6k 1.0E-03 19.2k 115.2k 1.0E-04 1.0E-05 1.0E-06 -85 © 2009 Microchip Technology Inc. ...
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... Rate BW – – kHz ΔTX Δf Δf Δf – 45 – 45 FSK FSK in kHz © 2009 Microchip Technology Inc. ) set- FSK 4.8 kbps 9.6 kbps 19.2 kbps BW – – – 67 Δf Δf – 45 – 45 – 45 FSK FSK FSK ...
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... Receiver Sensitivity over Ambient Temperature for 868 MHz -100 -103 -106 -109 -112 -115 -50 -25 DS70590B-page 86 Δ kHz, BW: 67 kHz) FSK Temperature (°C) Δ kHz, BW: 67 kHz) FSK Temperature (°C) Preliminary 2.2V 2.7V 3.3V 3.8V 100 2.2V 2.7V 3.3V 3.8V 100 © 2009 Microchip Technology Inc. ...
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... In the event, the full Microchip part number cannot be marked on one line, it Note: will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. Example 49XA/ST 0910 Preliminary ...
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... This section provides the technical details of the packages. 16-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70590B-page 88 Preliminary © 2009 Microchip Technology Inc. ...
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... Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc. Preliminary MRF49XA DS70590B-page 89 ...
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... MRF49XA 16-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70590B-page 90 Preliminary © 2009 Microchip Technology Inc. ...
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... Applicable when the RXCEN bit is cleared using the PMCREG. 3. These bits are internally latched and the other bits are only multiplexed out. TABLE A-1: RECOMMENDED FIFO PACKET STRUCTURES Length Preamble Minimum Length 4-8 bits (0x0A or 0x05) Recommended Length 8-12 bits (e.g., 0xAA or 0x55) © 2009 Microchip Technology Inc ...
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... MRF49XA NOTES: DS70590B-page 92 Preliminary © 2009 Microchip Technology Inc. ...
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... APPENDIX B: REVISION HISTORY Revision A (March 2009) This is the initial released version of this document. Revision B (June 2009) Major updates are done throughout the document. © 2009 Microchip Technology Inc. Preliminary MRF49XA DS70590B-page 93 ...
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... MRF49XA NOTES: DS70590B-page 94 Preliminary © 2009 Microchip Technology Inc. ...
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... Digital Operation ......................................................... 55 Data Indicator Output (DIO) ................................................ 13 Data Quality Indicator (DQI).......................................... 13, 56 Data Validity Blocks Data Indicator Output.................................................. 13 Data Quality Indicator ................................................. 13 Receive Signal Strength Indicator............................... 13 © 2009 Microchip Technology Inc. E Electrical Characteristics .................................................... 77 Errata .................................................................................... 3 Examples Frequency Deviation and BBBW Calculation ............. 54 External Reference Input .................................................... 10 F FIFO Interrupt ...
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... Power-on Reset Example ........................................... 43 Receiver FIFO Read................................................... 68 Sensitive Reset Disabled............................................ 45 Sensitive Reset Enabled............................................. 44 SPI .............................................................................. 82 STSREG Read Sequence .......................................... 91 TX Register Usage ..................................................... 67 Transmit Register ............................................................... 14 TX Register Buffered Data Transmission ........................... 64 Typical Applications .............................................................. Line Filtering................................................................ Wake-up Timer ................................................................... 14 WWW Address ................................................................... 97 WWW, On-Line Support ....................................................... 3 Preliminary © 2009 Microchip Technology Inc. ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
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... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70590B-page 98 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS70590B Preliminary © 2009 Microchip Technology Inc. ...
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... C to +85 ° C (Industrial) Temperature Range I Package ST = TSSOP (Lead Plastic Thin Shrink Small Outline, No Lead Tape and Reel © 2009 Microchip Technology Inc. XXX Example: a) MRF49XA-I/ST: Industrial temperature, Pattern TSSOP package. b) MRF49XAT-I/ST: Industrial temperature, TSSOP package, tape and reel. Preliminary MRF49XA . DS70590B-page 99 ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...