MRF49XAT-I/ST Microchip Technology, MRF49XAT-I/ST Datasheet - Page 43

• Manufacturer Part Number: MRF49XAT-I/ST
• Description: IC RF TXRX 433/868/915 16-TSSOP
• Manufacturer: Microchip Technology

Specifications of MRF49XAT-I/ST

• Package / Case: 16-TSSOP
• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FHSS, FSK
• Applications: Home / Industrial Automation, Remote Access, Security Alarms
• Power - Output: 7dbm
• Sensitivity: -110dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 11mA
• Current - Transmitting: 15mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 2
• Wireless Frequency: 433 MHz to 915 MHz
• Output Power: + 7 dBm
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Modulation: FHSS, FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 579-MRF49XAT-1/ST

REGISTER 2-17:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-1
R/W-0
—
CCB<15:8>: Command Code bits
The command code bits (11001100b) are serially sent to the microcontroller to identify the bits to be
written in the PLLCREG.
Unimplemented: Write as ‘0’
CBTC<1:0>: Clock Buffer Time Control bits
These bits control the rise and fall time for the clock buffer which is dependant on the output clock
frequency from the BCSREG.
11 = 5-10 MHz
10 = 3.3 MHz
01 = 2.5 MHz or less
00 = 2.5 MHz or less
Reserved: Masked to ‘1’
PDDS: Phase Detector Delay Switch bit
1 = Enables the phase detector delay function
0 = Disables the phase detector delay function
PLLDD: PLL Dithering Disable bit
1 = Disables PLL dithering
0 = Enables PLL dithering
Reserved: Write as ‘1’
PLLBWB: PLL Bandwidth bit
Enabling the bit configures higher data rates, faster settling and reduced phase noise; thus, resulting
in a better RF performance.
1 = -102 dBc/Hz, > 90 kbps (max 256 kbps)
0 = -107 dBc/Hz, < 90 kbps (max 86.2 kbps)
R/W-1
R/W-1
PLLCREG: PLL CONFIGURATION REGISTER (POR: 0xCC77)
CBTC<1:0>
r = reserved bit
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-1
R/W-0
R/W-1
Preliminary
r
CCB<15:8>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
R/W-0
PDDS
PLLDD
R/W-1
R/W-1
x = Bit is unknown
MRF49XA
R/W-0
R/W-1
r
DS70590B-page 41
PLLBWB
R/W-0
R/W-1
bit 8
bit 0