ATZB-24-A2 Atmel, ATZB-24-A2 Datasheet - Page 40

• Manufacturer Part Number: ATZB-24-A2
• Description: KIT MOD 802.15.4/ZIGB 2.4GHZ ANT
• Manufacturer: Atmel

Specifications of ATZB-24-A2

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: Home/Building Automation, Industrial Control and Monitoring
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 19mA
• Current - Transmitting: 18mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kBytes Flash, 8kBytes RAM, 4kBytes EEPROM
• Antenna Connector: On-Board, Chip
• Operating Temperature: -40°C ~ 85°C
• Package / Case: Module
• Tool Type: Wireless Development Kit
• Core Architecture: AVR
• Cpu Core: AVR 8
• Data Bus Width: 8 bit
• Description/function: ZigBit 2.4 GHz Dual Chip Antenna
• Wireless Frequency: 2.4 GHz
• Interface Type: UART, I2C, SPI
• Operating Voltage: 1.8 V to 3.6 V
• Output Power: 3 dBm
• Antenna: Chip Antenna
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24. Crypto Engine
24.1
24.2
8069Q–AVR–12/10
Features
Overview
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The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two com-
monly used encryption standards. These are supported through an AES peripheral module and
a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and
DES encrypted communication and data storage.
DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte
data blocks must be loaded into the Register file, and then DES must be executed 16 times to
encrypt/decrypt the data block.
The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key.
The key and data must be loaded into the key and state memory in the module before encryp-
tion/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is
done and decrypted/encrypted data can be read out, and an optional interrupt can be generated.
The AES Crypto Module also has DMA support with transfer triggers when encryption/decryp-
tion is done and optional auto-start of encryption/decryption when the state memory is fully
loaded.
Data Encryption Standard (DES) CPU instruction
Advanced Encryption Standard (AES) Crypto module
DES Instruction
AES Crypto Module
– Encryption and Decryption
– Single-cycle DES instruction
– Encryption/Decryption in 16 clock cycles per 8-byte block
– Encryption and Decryption
– Support 128-bit keys
– Support XOR data load mode to the State memory for Cipher Block Chaining
– Encryption/Decryption in 375 clock cycles per 16-byte block
XMEGA A4
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