ATZB-24-A2 Atmel, ATZB-24-A2 Datasheet - Page 42

KIT MOD 802.15.4/ZIGB 2.4GHZ ANT

ATZB-24-A2

Manufacturer Part Number
ATZB-24-A2
Description
KIT MOD 802.15.4/ZIGB 2.4GHZ ANT
Manufacturer
Atmel
Datasheets

Specifications of ATZB-24-A2

Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
Home/Building Automation, Industrial Control and Monitoring
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
19mA
Current - Transmitting
18mA
Data Interface
PCB, Surface Mount
Memory Size
128kBytes Flash, 8kBytes RAM, 4kBytes EEPROM
Antenna Connector
On-Board, Chip
Operating Temperature
-40°C ~ 85°C
Package / Case
Module
Tool Type
Wireless Development Kit
Core Architecture
AVR
Cpu Core
AVR 8
Data Bus Width
8 bit
Description/function
ZigBit 2.4 GHz Dual Chip Antenna
Wireless Frequency
2.4 GHz
Interface Type
UART, I2C, SPI
Operating Voltage
1.8 V to 3.6 V
Output Power
3 dBm
Antenna
Chip Antenna
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATZB-24-A2
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATZB-24-A2R
Manufacturer:
CIRRUS
Quantity:
201
8069Q–AVR–12/10
Figure 25-1. ADC overview
Each ADC has four MUX selection registers with a corresponding result register. This means
that four channels can be sampled within 1.5 µs without any intervention by the application other
than starting the conversion. The results will be available in the result registers.
The ADC may be configured for 8- or 12-bit resolution, reducing the minimum conversion time
(propagation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit resolution.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
Channel C MUX selection
Channel D MUX selection
Channel A MUX selection
Channel B MUX selection
1-64 X
Reference selection
Configuration
ADC
Trigger
Event
Channel A
Channel B
Channel C
Channel D
Register
Register
Register
Register
XMEGA A4
42

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