CYWUSB6934-48LFC

Manufacturer Part NumberCYWUSB6934-48LFC
DescriptionIC WIRELESS USB 2.4GHZ 48VQFN
ManufacturerCypress Semiconductor Corp
CYWUSB6934-48LFC datasheets
 


Specifications of CYWUSB6934-48LFC

Frequency2.4GHzData Rate - Maximum62.5kbps
Modulation Or ProtocolDSSS, GFSKApplicationsHID, PC, Peripheral Gaming Devices
Power - Output0dBmSensitivity-90dBm
Voltage - Supply2.7 V ~ 3.6 VData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature0°C ~ 70°C
Package / Case48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFNOperating Temperature (min)0C
Operating Temperature (max)70COperating Temperature ClassificationCommercial
Operating Supply Voltage (min)2.7VOperating Supply Voltage (typ)3V
Operating Supply Voltage (max)3.6VLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Memory Size-Current - Transmitting-
Current - Receiving-Other names428-1581
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WirelessUSB™ LS 2.4-GHz DSSS Radio SoC
1.0
Features
• 2.4-GHz radio transceiver
• Operates in the unlicensed Industrial, Scientific, and
Medical (ISM) band (2.4 GHz–2.483 GHz)
• -90-dBm receive sensitivity
• Up to 0 dBm output power
• Range of up to 10 meters or more
• Data throughput of up to 62.5 kbits/sec
• Highly integrated low cost, minimal number of external
components required
• Dual DSSS reconfigurable baseband correlators
• SPI microcontroller interface (up to 2-MHz data rate)
• 13-MHz
50-ppm input clock operation
• Low standby current < 1 µA
• Integrated 30-bit Manufacturing ID
• Operating voltage from 2.7V to 3.6V
• Operating temperature from 0° to 70°C
• Offered in a small footprint 48 Quad Flat Pack No Leads
(QFN)
DIOVAL
DIO
SERDES
IRQ
SS
SCK
Digital
MISO
SERDES
MOSI
RESET
P D
Figure 3-1. CYWUSB6932/CYWUSB6934 Simplified Block Diagram
Cypress Semiconductor Corporation
Document 38-16007 Rev. *G
2.0
Functional Description
The CYWUSB6932/CYWUSB6934 Integrated Circuits (ICs)
are highly integrated 2.4-GHz Direct Sequence Spread
Spectrum (DSSS) Radio System-on-Chip (SoC) ICs. From the
Serial Peripheral Interface (SPI) to the antenna, these ICs are
single-chip 2.4-GHz DSSS Gaussian Frequency Shift Keying
(GFSK) baseband modems that connect directly to a micro-
controller via simple serial interface.
The CYWUSB6932 transmit-only IC and the CYWUSB6934
transceiver IC are available in a small footprint 48-pin QFN
package.
3.0
Applications
• PC Human Interface Devices (HIDs)
Mice
Keyboards
Joysticks
• Peripheral Gaming Devices
Game Controllers
Console Keyboards
• General
Presenter Tools
Remote Controls
Consumer Electronics
Barcode Scanners
POS Peripherals
Toys
GFSK
DSSS
Modulator
Baseband
A
A
DSSS
Baseband
GFSK
B
B
Demodulator
Synthesizer
3901 North First Street
CYWUSB6932
CYWUSB6934
RFOUT
RFIN
CY WUSB6934 Only
,
San Jose
CA 95134
408-943-2600
Revised November 15, 2004

CYWUSB6934-48LFC Summary of contents

  • Page 1

    ... Serial Peripheral Interface (SPI) to the antenna, these ICs are single-chip 2.4-GHz DSSS Gaussian Frequency Shift Keying (GFSK) baseband modems that connect directly to a micro- controller via simple serial interface. The CYWUSB6932 transmit-only IC and the CYWUSB6934 transceiver IC are available in a small footprint 48-pin QFN package. 3.0 Applications • ...

  • Page 2

    ... ETSI EN 301 489-1 V1.4.1, ETSI EN 300 328-1 V1.3.1 (European Countries); FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB STD-T66 (Japan). The CYWUSB6934 IC contains a 2.4-GHz radio transceiver, a GFSK modem and a dual DSSS reconfigurable baseband. The CYWUSB6932 IC contains a 2.4-GHz radio transmit-only, a GFSK modem and a DSSS baseband. The radio and baseband are both code- and frequency-agile ...

  • Page 3

    ... Drive Level: 10 uW–100 uW 4.7 Receive Signal Strength Indicator (RSSI) The RSSI register (Reg 0x22) (applies only to the CYWUSB6934 IC) returns the relative signal strength of the ON-channel signal power and can be used to: 1. Determine the connection quality 2. Determine the value of the noise floor 3 ...

  • Page 4

    ... Address Figure 5-1. SPI Transaction Format Figure 5-2. SPI Single Read Sequence Figure 5-3. SPI Burst Read Sequence data from Figure 5-4. SPI Single Write Sequence from Figure 5-5. SPI Burst Write Sequence CYWUSB6932 CYWUSB6934 Byte 1+N [7:0] Data fro Page ...

  • Page 5

    ... Interrupts The CYWUSB6932/CYWUSB6934 ICs feature three sets of interrupts: transmit, receive (CYWUSB6934 only), and a wake interrupt. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. In transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. ...

  • Page 6

    ... Buttons Figure 6-1. CYWUSB6932 Transmit-Only Battery-Powered Device PCB Trace Antenna 0.1 F 2.0 pF 2.0 pF 1.2 pF 3.3 nH RFOUT RFIN 2 irelessUSB LS 13MHz Cry stal Figure 6-2. CYWUSB6934 USB Bridge Transceiver Document 38-16007 Rev. *G 3.3 V Vcc RESET PD IRQ SPI 4 3.3V LDO 0.1µF 1µF RESET PD IRQ 2 ...

  • Page 7

    ... Register Descriptions displays the list of Table 7-1 CYWUSB6932/CYWUSB6934 ICs that are addressable through the SPI interface. All registers are read and writable, except where noted. Table 7-1. CYWUSB6932/CyWUSB6934 Register Map Register Name Revision ID Control Data Rate Configuration SERDES Control Receive SERDES Interrupt Enable REG_RX_INT_EN ...

  • Page 8

    ... Reserved This bit is reserved and should be written with a zero. Document 38-16007 Rev. *G Figure 7-1. Revision ID Register REG_ID Figure 7-2. Control REG_CONTROL Bypass Internal Auto Internal Syn Lock Signal PA Disable CYWUSB6932 CYWUSB6934 Default: 0x07 Product ID Default: 0x00 Internal PA Reserved Reserved Enable Page ...

  • Page 9

    ... Not Valid • 011 – Not Valid • 111 – Not Valid. Document 38-16007 Rev. *G REG_DATA_RATE Figure 7-3. Data Rate Figure 7-4. Configuration REG_CONFIG Reserved CYWUSB6932 CYWUSB6934 Default: 0x00 Code Width Data Rate Sample Rate Default: 0x01 IRQ Pin Select Page ...

  • Page 10

    ... SERDES Data Register and can also be used to generate interrupts the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. Document 38-16007 Rev. *G REG_SERDES_CTL SERDES Enable Figure 7-5. SERDES Control CYWUSB6932 CYWUSB6934 Default: 0x03 EOF Length Page ...

  • Page 11

    ... This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. Document 38-16007 Rev. *G REG_RX_INT_EN Full B Underflow A Figure 7-6. Receive SERDES Interrupt Enable CYWUSB6932 CYWUSB6934 Default: 0x00 Overflow A EOF A Full A Page ...

  • Page 12

    ... TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These registers are read-only. Document 38-16007 Rev. *G REG_RX_INT_STAT Full B Valid A Figure 7-7. Receive SERDES Interrupt Status CYWUSB6932 CYWUSB6934 Default: 0x00 2 1 Flow Violation EOF A Full A A [4] Page ...

  • Page 13

    ... Document 38-16007 Rev. *G REG_RX_DATA_A Data Figure 7-8. Receive SERDES Data A REG_RX_VALID_A Valid Figure 7-9. Receive SERDES Valid A REG_RX_DATA_B Data Figure 7-10. Receive SERDES Data B Figure 7-11. Receive SERDES Valid B REG_RX_VALID_B Valid CYWUSB6932 CYWUSB6934 Default: 0x00 Default: 0x00 Default: 0x00 Default: 0x00 Page ...

  • Page 14

    ... The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer and it's safe to load the next byte Document 38-16007 Rev. *G REG_TX_INT_EN Underflow Figure 7-12. Transmit SERDES Interrupt Enable CYWUSB6932 CYWUSB6934 Default: 0x00 Overflow Done Empty Page ...

  • Page 15

    ... TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only. Document 38-16007 Rev. *G REG_TX_INT_STAT Underflow Figure 7-13. Transmit SERDES Interrupt Status CYWUSB6932 CYWUSB6934 Default: 0x00 Overflow Done Empty Page ...

  • Page 16

    ... Data Figure 7-14. Transmit SERDES Data REG_TX_VALID Valid Figure 7-15. Transmit SERDES Valid REG_PN_CODE Address 0x17 Address 0x16 Figure 7-16. PN Code Address 0x13 Address 0x12 CYWUSB6932 CYWUSB6934 Default: 0x00 2 1 Default: 0x00 2 1 Default: 0x1E8B6A3DE0E9B222 Address 0x15 Address 0x11 Page ...

  • Page 17

    ... A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications. Document 38-16007 Rev. *G REG_THRESHOLD_L Threshold Low Figure 7-17. Threshold Low REG_THRESHOLD_H Threshold High Figure 7-18. Threshold High REG_WAKE_EN Reserved Figure 7-19. Wake Enable CYWUSB6932 CYWUSB6934 Default: 0x08 Default: 0x38 Default: 0x00 Wakeup En- able Page ...

  • Page 18

    ... The Reset bit is used to generate a self-clearing device reset Device Reset. All registers are restored to their default values Device Reset. Document 38-16007 Rev. *G REG_WAKE_STAT Reserved Figure 7-20. Wake Status REG_ANALOG_CTL Reserved Reserved Figure 7-21. Analog Control CYWUSB6932 CYWUSB6934 Default: 0x01 Wakeup Status Default: 0x00 Output PA Invert Reset Enable Page ...

  • Page 19

    ... The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7=1). See Section 4.7 for more details. Document 38-16007 Rev. *G REG_CHANNEL Channel Figure 7-22. Channel REG_RSSI Valid REG_PA Figure 7-24. PA Bias CYWUSB6932 CYWUSB6934 Default: 0x00 Default: 0x00 RSSI [7] Default: 0x00 Bias Page ...

  • Page 20

    ... These bits are reserved and should be written with zeroes. Document 38-16007 Rev. *G REG_CRYSTAL_ADJ Crystal Adjust Figure 7-25. Crystal Adjust REG_VCO_CAL Reserved Figure 7-26. VCO Calibration REG_PWR_CTL Reserved Figure 7-27. Reg Power Control CYWUSB6932 CYWUSB6934 Default: 0x00 Default: 0x00 Default: 0x00 Page ...

  • Page 21

    ... Figure 7-29. Clock Manual REG_CLOCK_ENABLE Manual Clock Enables Figure 7-30. Clock Enable REG_SYN_LOCK_CNT Count Figure 7-31. Synthesizer Lock Count REG_MID Address 0x3E Address 0x3D Figure 7-32. Manufacturing ID CYWUSB6932 CYWUSB6934 Default: 0x00 2 1 Default: 0x00 2 1 Default: 0x00 2 1 Default: 0x64 Address 0x3C Page ...

  • Page 22

    ... N/A Crystal Input . (refer to Section 4.6 ). Output System Clock . Buffered 13-MHz system clock. N/A Power Down . Asserting this input (low), will put the CYWUSB6932/CYWUSB6934 in the Suspend Mode (X13OUT is 0 when PD is Low). N/A Active LOW Reset . Device reset. Input PACTL . External Power Amplifier control. Pull-down or make output. ...

  • Page 23

    ... E-PAD BOTTOM SIDE ** CYWUSB6934 Only Figure 8-1. CYWUSB6934/CYWUSB6932, 48 QFN – Top View Document 38-16007 Rev. *G CYWUSB6934/CYWUSB6932 Top View RFOUT 5 CYWUSB6934/CYWUSB6932 QFN CYWUSB6932 CYWUSB6934 X13IN 34 PACTL X13OUT 25 SCK Page ...

  • Page 24

    ... Average Icc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10ms using the WirelessUSB LS 2-way protocol. Document 38-16007 Rev. *G Description Conditions < HIGH [12] no handshake [13] with handshaking CYWUSB6932 CYWUSB6934 [11] Min. Typ. Max. 2.7 3.0 3.6 = –100.0µA V –0 –2.0 mA 2.4 3.0 = 2.0 mA ...

  • Page 25

    ... SCK must start low, otherwise the success of SPI transactions are not guaranteed. Document 38-16007 Rev. *G Description fro Figure 12-1. SPI Timing Diagram t t SCK_LO S CK_H I (B URST READ) th every 9 S CK_H I data T_VAL CYWUSB6932 CYWUSB6934 Min. Typ. Max. Unit 476 ns 238 ns 158 ns 158 [16 [16] [16] 77 174 ns ...

  • Page 26

    ... Document 38-16007 Rev. *G Description Figure 12-3. DIO Receive Timing Diagram _IR _IR Q _LO data _DIO V A L_S AL_ HLD Figure 12-4. DIO Transmit Timing Diagram CYWUSB6932 CYWUSB6934 Min. Typ. Max. 2.1 2 Min. Typ. Max. -0.01 6.1 -0.01 8.2 -0.01 16.1 -0.01 6.1 -0 ...

  • Page 27

    ... C = –67 dBm C = –67 dBm C = –67 dBm [18 –67 dBm [18 –67 dBm C = –64 dBm 5,10 MHz seven steps, monotonic PN Code Pattern 10101010 PN Code Pattern 11110000 100-kHz resolution bandwidth, –6 dBc CYWUSB6932 CYWUSB6934 Min. Typ. Max. Unit 2.400 2.483 GHz –3 ) –90 dBm –20 –10 ...

  • Page 28

    ... Conditions V [22] [23] [25] assert (wake interrupt) to within ±10 ppm to within ±10 ppm Figure 12-5. Power On Reset/Reset Timing t WAKE t WAKE_INT Figure 12-6. Sleep / Wake Timing CYWUSB6932 CYWUSB6934 [26] Min. Typ Max. 2000 1 @ 2.7V 1300 cc 1 1300 2000 10 50 2000 2100 2100 ...

  • Page 29

    ... 3.00 CC Figure 12-7. AC Test Loads and Waveforms for Digital Pins 13.0 Ordering Information Table 13-1. Ordering Information Part Number Radio CYWUSB6932-48LFXC Transmitter CYWUSB6934-48LFXC Transceiver 14.0 Package Description 6.90 7.10 6.70 6. 0.80 DIA. TOP VIEW DIMENSIONS IN mm MIN. MAX. REFERENCE JEDEC MO-220 PKG ...

  • Page 30

    ... Document History Page Document Title: CYWUSB6932/CYWUSB6934 WirelessUSB™ LS 2.4-GHz DSSS Radio SoC Document Number: 38-16007 REV. ECN NO. Issue Date ** 123907 01/20/03 *A 125470 04/28/03 *B 127076 07/30/03 *C 128886 08/04/03 *D 129180 12/04/03 *E 131851 12/15/03 *F 241471 See ECN *G 284810 See ECN Document 38-16007 Rev. *G Orig. of ...