CYWUSB6934-48LFC Cypress Semiconductor Corp, CYWUSB6934-48LFC Datasheet - Page 26

• Manufacturer Part Number: CYWUSB6934-48LFC
• Description: IC WIRELESS USB 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6934-48LFC

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: HID, PC, Peripheral Gaming Devices
• Power - Output: 0dBm
• Sensitivity: -90dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 428-1581

Table 12-2. DIO Interface
Document 38-16007 Rev. *G
t
t
t
t
t
t
t
t
t
t
TX_DIOVAL_SU
TX_DIO_SU
TX_DIOVAL_HLD
TX_DIO_HLD
TX_IRQ_HI
TX_IRQ_LO
RX_DIOVAL_VLD
RX_DIO_VLD
RX_IRQ_HI
RX_IRQ_LO
Parameter
Transmit
Receive
D IO V A L
D IO V A L
D IO /
IR Q
D IO /
IR Q
DIOVAL Set-up Time
DIO Set-up Time
DIOVAL Hold Time
DIO Hold Time
Minimum IRQ High Time - 32 chips/bit DDR
Minimum IRQ High Time - 32 chips/bit
Minimum IRQ High Time - 64 chips/bit
Minimum IRQ Low Time - 32 chips/bit DDR
Minimum IRQ Low Time - 32 chips/bit
Minimum IRQ Low Time - 64 chips/bit
DIOVAL Valid Time - 32 chips/bit DDR
DIOVAL Valid Time - 32 chips/bit
DIOVAL Valid Time - 64 chips/bit
DIO Valid Time - 32 chips/bit DDR
DIO Valid Time - 32 chips/bit
DIO Valid Time - 64 chips/bit
Minimum IRQ High Time - 32 chips/bit DDR
Minimum IRQ High Time - 32 chips/bit
Minimum IRQ High Time - 64 chips/bit
Minimum IRQ Low Time - 32 chips/bit DDR
Minimum IRQ Low Time - 32 chips/bit
Minimum IRQ Low Time - 64 chips/bit
t
R X _ IR Q _ H I
d a ta
Figure 12-4. DIO Transmit Timing Diagram
Figure 12-3. DIO Receive Timing Diagram
t
T X _DIO V A L_S U
t
Description
TX _D IO _S U
t
T X _IR Q _H I
t
R X _ D IO V A L _ V L D
t
R X _ D IO _ V L D
t
data
R X _ IR Q _ L O
t
TX _IR Q _LO
t
TX _D IO V AL_ HLD
t
TX _D IO _H LD
-0.01
-0.01
-0.01
-0.01
-0.01
-0.01
Min.
Min.
2.1
2.1
0
0
d a ta
Typ.
Typ.
16
32
16
32
16
32
8
8
1
1
1
8
data
CYWUSB6932
CYWUSB6934
Max.
Max.
16.1
16.1
8.2
6.1
8.2
6.1
Page 26 of 30
d a ta
Unit
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs