SP7651ER-L Exar Corporation, SP7651ER-L Datasheet - Page 8

• Manufacturer Part Number: SP7651ER-L
• Description: IC BUCK REG 900KHZ 26DFN
• Manufacturer: Exar Corporation
• Series: Power Blox™r
• Type: Step-Down (Buck)r

Specifications of SP7651ER-L

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 V ~ 19 V
• Current - Output: 3A
• Frequency - Switching: 900kHz
• Voltage - Input: 2.5 V ~ 20 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: 26-VFDFN Exposed Pad
• Primary Input Voltage: 20V
• No. Of Outputs: 1
• Output Voltage: 19V
• Output Current: 3A
• No. Of Pins: 26
• Operating Temperature Range: -40°C To +85°C
• Supply Voltage Range: 2.5V To 20V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Output Capacitor Selection
The required ESR (Equivalent Series Re-
sistance) and capacitance drive the selec-
tion of the type and quantity of the output
capacitors. The ESR must be small enough
that both the resistive voltage deviation due
to a step change in the load current and
the output ripple voltage do not exceed
the tolerance limits expected on the output
voltage. During an output load transient,
the output capacitor must supply all the ad-
ditional current demanded by the load until
the SP7651 adjusts the inductor current to
the new value.
In order to maintain V
must be large enough so that the output
voltage is held up while the inductor current
ramps up or down to the value correspond-
ing to the new load current. Additionally, the
ESR in the output capacitor causes a step
in the output voltage equal to the current.
Because of the fast transient response and
inherent 100% to 0% duty cycle capability
provided by the SP765 when exposed to
an output load transient, the output capacitor
is typically chosen for ESR, not for capaci-
tance value.
The ESR of the output capacitor, combined
with the inductor ripple current, is typically
the main contributor to output voltage ripple.
The maximum allowable ESR required to
maintain a specified output voltage ripple
can be calculated by:
where:
∆V
Ripple
I
rent
The total output ripple is a combination of
the ESR and the output capacitance value
and can be calculated as follows:
Rev J: 3/4/07
PK-PK
∆V
OUT
OUT
= Peak-to-Peak Inductor Ripple Cur-
= Peak-to-Peak Output Voltage
R
=
esr
(
I
PP
C
≤
OUT
( – D)
∆V
I
F
pk
S
out
-
OUT,
pk
)
SP765 Wide Input Voltage Range 3A, 900kHz, Buck Regulator
2
the capacitance
+ (I
PP
R
ESR
)
2
8
F
D = Duty Cycle
C
Input Capacitor Selection
The input capacitor should be selected for
ripple current rating, capacitance and volt-
age rating. The input capacitor must meet
the ripple current requirement imposed
by the switching current. In continuous
conduction mode, the source current of
the high-side MOSFET is approximately
a square wave of duty cycle V
Most of this current is supplied by the
input bypass capacitors. The RMS value
of input capacitor current is determined at
the maximum output current and under the
assumption that the peak-
to-peak inductor ripple current is low; it is given
by:
The worse case occurs when the duty cycle
D is 50% and gives an RMS current value
equal to I
adequate ripple current rating to ensure reli-
able operation.
The power dissipated in the input capaci-
tor is:
This can become a significant part of power
losses in a converter and hurt the overall
energy transfer efficiency. The input volt-
age ripple primarily depends on the input
capacitor ESR and capacitance. Ignoring
the inductor ripple current, the input voltage
ripple can be determined by:
The capacitor type suitable for the output
capacitors can also be used for the input ca-
pacitors. However, exercise extra caution
S
OUT
= Switching Frequency
P
= Output Capacitance Value
∆V
I
I
CIN(rms)
out
on
OUT
in
APPLICATIONS INFORMATION
= i
=i
(
max
/2. Select input capacitors with
2
out
= I
on
F
OUT(max)
) V
s
(
(
rms
max
c
out
in
© Copyright 2007 Sipex Corporation
V
) r
) r
in
√
(V
D( - D)
2
esr
esr
in
-V
(
(
OUT
cin
cin
out
/V
)
) +
IN
)
.