AD7298BCPZ Analog Devices Inc, AD7298BCPZ Datasheet - Page 17

IC ADC 12BIT SPI/SRL 1M 20LFCSP

AD7298BCPZ

Manufacturer Part Number
AD7298BCPZ
Description
IC ADC 12BIT SPI/SRL 1M 20LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD7298BCPZ

Data Interface
Serial, SPI™
Featured Product
AD7298 ADC with Temperature Sensor
Number Of Bits
12
Sampling Rate (per Second)
1M
Number Of Converters
1
Power Dissipation (max)
22.7mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-WFQFN, CSP Exposed Pad
Resolution (bits)
12bit
Sampling Rate
1MSPS
Input Channel Type
Single Ended
Supply Voltage Range - Digital
1.65V To 3.6V
Supply Current
5.8mA
Digital Ic Case
RoHS Compliant
Supply Voltage Range - Analog
1.65V To 3.6V
Digital Ic Case Style
LFCSP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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MODES OF OPERATION
The AD7298 offers different modes of operation, that are
designed to provide additional flexibility for the user. These
options can be chosen by programming the content of the
control register to select the desired mode.
TRADITIONAL MULTICHANNEL MODE OF
OPERATION
The AD7298 can operate as a traditional multichannel
ADC, where each serial transfer selects the next channel for
conversion. One must write to the control register to configure
and select the desired input channel prior to initiating any
conversions. In the traditional mode of operation, the CS signal
is used to frame the first write to the converter on the DIN pin.
In this mode of operation, the REPEAT bit in the control
register is set to a low logic level, 0, thus the REPEAT function
is not in use. The data, which appears on the DOUT pin during
the initial write to the control register, is invalid. The first CS
falling edge initiates a write to the control register to configure
the device; a conversion is then initiated for the selected analog
input channel (V
DOUT
SCLK
DIN
CS
1
REGISTER CHANNEL 1 SELECTED
DATA WRITTEN TO CONTROL
DOUT
DOUT
SCLK
SCLK
DIN
DIN
CS
CS
INVALID DATA
IN0
) on the subsequent (2
1
REGISTER CH 1 AND 2 SELECTED
1
Figure 26. Configuring a Conversion and Read with the AD7298. Numerous channels selected for conversion.
DATA WRITTEN TO CONTROL
12
Figure 25. Configuring a Conversion and Read with the AD7298. One channel selected for conversion.
CONVERSION RESULT
CONTROL REGISTER
NO WRITE TO THE
FOR CHANNEL 2
INVALID DATA
16
12
nd
1
REGISTER CHANNEL 4 SELECTED
) CS falling edge; the
DATA WRITTEN TO CONTROL
16
16
INVALID DATA
1
1
CONVERSION RESULT
CONTROL REGISTER
CONTROL REGISTER
Rev. A | Page 17 of 24
NO WRITE TO THE
NO WRITE TO THE
FOR CHANNEL 5
INVALID DATA
16
third CS falling edge will have the result (V
reading. The AD7298 operates with one cycle latency, thus the
conversion result corresponding to each conversion is available
one serial read cycle after the cycle in which the conversion was
initiated.
As the device operates with one cycle latency, the control
register configuration sets up the configuration for the next
conversion, which is initiated on the next CS falling edge, but
the first bit of the corresponding result is not clocked out until
the subsequent falling CS edge, as shown in Figure 25.
If more than one channel is selected in the control register, the
AD7298 converts all selected channels sequentially in ascending
order on successive CS falling edges. Once all the selected
channels in the control register are converted, the AD7298
ceases converting until the user rewrites to the control register
to select the next channel for conversion. This operation is
shown in Figure 26. DOUT returns all 1s if the sequence of
conversions is completed or if no channel is selected.
1
16
16
CONVERSION RESULT
CONTROL REGISTER
NO WRITE TO THE
FOR CHANNEL 1
1
REGISTER CHANNEL 5 SELECTED
DATA WRITTEN TO CONTROL
CONVERSION RESULT
FOR CHANNEL 1
16
1
16
CONVERSION RESULT
CONTROL REGISTER
NO WRITE TO THE
FOR CHANNEL 4
IN2
) available for
AD7298
16

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