WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet
WM8352GEB/V
Specifications of WM8352GEB/V
Related parts for WM8352GEB/V
WM8352GEB/V Summary of contents
Page 1
... BGA package, 0.5mm ball pitch APPLICATIONS TM series of audio and • Portable Audio and Media players • Portable Navigation Devices • Portable systems powered by single-cell lithium batteries http://www.wolfsonmicro.com/enews WM8352 Production Data, March 2010, Rev 4.2 Copyright ©2010 Wolfson Microelectronics plc ...
Page 2
WM8352 TYPICAL APPLICATIONS The WM8352 is a complete audio and power management solution for portable media devices. The device incorporates four programmable step-down switching regulators, two step-up switching regulators, a full-featured battery charger, four Low Drop-Out (LDO) voltage regulators which ...
Page 3
Production Data BLOCK DIAGRAM w WM8352 PD, March 2010, Rev 4.2 3 ...
Page 4
WM8352 DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 TYPICAL APPLICATIONS ..................................................................................... 2 BLOCK DIAGRAM ................................................................................................. 3 TABLE OF CONTENTS ......................................................................................... 4 1 PIN CONFIGURATION .................................................................................. 9 2 ORDERING INFORMATION .......................................................................... 9 3 PIN DESCRIPTION ...................................................................................... 10 4 THERMAL CHARACTERISTICS ...
Page 5
Production Data 12.1 GENERAL DESCRIPTION ............................................................................. 45 12.1.1 CLOCKING THE AUDIO CODEC ........................................................................................ 46 12.1.2 CLOCKING THE DC-DC CONVERTERS ............................................................................ 46 12.1.3 INTERNAL RC OSCILLATOR .............................................................................................. 46 12.2 CRYSTAL OSCILLATOR ................................................................................ 46 12.3 CLOCKING AND SAMPLE RATES ................................................................ 47 12.3.1 ...
Page 6
WM8352 13.12.2 MICROPHONE DETECTION ............................................................................................. 100 13.12.3 MID-RAIL REFERENCE (VMID) ........................................................................................ 101 13.12.4 ANTI-POP CONTROL ........................................................................................................ 102 13.12.5 UNUSED ANALOGUE INPUTS/OUTPUTS ....................................................................... 103 13.12.6 ZERO CROSS TIMEOUT .................................................................................................. 105 13.12.7 INTERRUPTS AND FAULT PROTECTION ....................................................................... 105 14 POWER MANAGEMENT SUBSYSTEM ...
Page 7
Production Data 16.3 OPEN-DRAIN LED OUTPUTS ..................................................................... 151 16.4 LED DRIVER CONNECTIONS ..................................................................... 151 17 POWER SUPPLY CONTROL .................................................................... 152 17.1 GENERAL DESCRIPTION ........................................................................... 152 17.2 BATTERY POWERED OPERATION ............................................................ 153 17.3 WALL ADAPTOR (LINE) POWERED OPERATION ..................................... 153 17.4 ...
Page 8
WM8352 24.2 FIRST-LEVEL INTERRUPTS ....................................................................... 199 24.3 SECOND-LEVEL INTERRUPTS .................................................................. 200 24.3.1 OVERCURRENT INTERRUPT .......................................................................................... 200 24.3.2 UNDERVOLTAGE INTERRUPTS ...................................................................................... 200 24.3.3 CURRENT SINK (LED DRIVER) INTERRUPTS ................................................................ 201 24.3.4 EXTERNAL INTERRUPTS ................................................................................................ 202 24.3.5 CODEC INTERRUPTS ...................................................................................................... 202 24.3.6 ...
Page 9
... DC-DC converters LDO voltage regulators Power m anagem ent functions Analogue pins for audio codec Digital pins for audio codec Quiet ground Others 2 ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8352GEB/V -25°C to +85°C WM8352GEB/RV -25°C to +85°C Note: Reel quantity = 2,200 PG1 ...
Page 10
WM8352 3 PIN DESCRIPTION Notes: Pins are listed in alphabetical order by name. NAME LOCATION(S) ADCDATA M7 AUX1 H11 AUX2 J13 AUX3 H13 AUX4 C9 AVDD M8 BATT E1, E2, D2 BCLK L8 CREF H3 Analogue Output CONF0 J1 CONF1 ...
Page 11
Production Data NAME LOCATION(S) HPVDD K13 IN1LN L11 IN1LP N10 IN1RN N13 IN1RP N12 IN2L M10 IN2R N11 IN3L L10 IN3R IRQ L4 ISINKA E11 Analogue Output ISINKB E12 Analogue Output L1 A5 C13 L3 ...
Page 12
WM8352 NAME LOCATION(S) REFGND N8 RREF J3 Analogue Output /RST L2 SCLK N2 SDATA M3 SINKGND E13 SWVRTC L3 Analogue Output USB G1, G2, G3 VINA G13 VINB F13 VMID N9 VOUT1 H12 Analogue Output VOUT2 G11 Analogue Output VOUT3 ...
Page 13
Production Data 4 THERMAL CHARACTERISTICS Thermal analysis must be performed in the intended application to prevent the WM8352 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of ...
Page 14
WM8352 5 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical ...
Page 15
Production Data 6 RECOMMENDED OPERATING CONDITIONS PARAMETER Digital Supply Range (Core) DCVDD Digital Supply Range (Buffer) DBVDD Headphone Supply Range HPVDD Analogue Supply Range AVDD Line Input Source LINE Battery Input Source BATT USB Input Source USB LDO Input Source ...
Page 16
WM8352 7 ELECTRICAL CHARACTERISTICS 7.1 HI-FI AUDIO CODEC Test Conditions DCVDD = 1.8V, AVDD = HPVDD = 3.3V, T PARAMETER Microphone Preamp Inputs (IN1LP, IN1LN, IN1RP, IN1RN) Full-scale Input Signal Level (0dB) – note this changes with AVDD Mic preamp ...
Page 17
Production Data Test Conditions DCVDD = 1.8V, AVDD = HPVDD = 3.3V, T PARAMETER Headphone Output (OUT1L, OUT1R, OUT2L, OUT2R) 0dB full scale output voltage Signal to Noise Ratio Total Harmonic Distortion (Note 3) OUT3/OUT4 outputs (with 10kΩ / 50pF ...
Page 18
WM8352 7.2 DC-DC STEP UP CONVERTER ELECTRICAL CHARACTERISTICS Test Conditions T = +25ºC unless otherwise noted. A PARAMETER SYMBOL DC-DC2 and DC-DC5 when used as converter Input voltage V IN range when used as switch Output voltage by default V ...
Page 19
Production Data 7.3 DC-DC STEP DOWN CONVERTER ELECTRICAL CHARACTERISTICS Test Conditions 1.8V +25ºC unless otherwise noted. IN OUT A PARAMETER SYMBOL DC-DC1 and DC-DC6 Input Voltage V IN Output Voltage V OUT VOUT ...
Page 20
WM8352 Test Conditions 1.8V +25ºC unless otherwise noted. IN OUT A PARAMETER SYMBOL DC-DC3 and DC-DC4 Input Voltage V IN Output Voltage V OUT VOUT Accuracy V V OUT IN V OUT / ...
Page 21
Production Data 7.4 LDO REGULATOR ELECTRICAL CHARACTERISTICS Test Conditions 1.8V +25ºC unless otherwise noted. IN OUT A PARAMETER LDO1 to LDO4 (WM8352 in ACTIVE State) Input Voltage Output voltage Regulation Accuracy Dropout Voltage ...
Page 22
WM8352 7.5 BATTERY CHARGER Test Conditions T = +25ºC unless otherwise noted. A PARAMETER SYMBOL General Wall adaptor voltage USB voltage Target voltage Defective battery threshold End of Charge Current Trickle Charging Trickle charge initiation threshold (WM8352 starts trickle charging ...
Page 23
Production Data 7.7 LED DRIVERS Test Conditions T = +25ºC unless otherwise noted. A PARAMETER ISINKA, ISINKB Sink Current ISINKC, ISINKD, ISINKE Sink Current Output voltage drop 7.8 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) Test Conditions T = +25ºC unless ...
Page 24
WM8352 7.9 DIGITAL INTERFACES Test Conditions T = +25ºC unless otherwise noted. A PARAMETER SDA, SCLK, MCLK, BCLK, LRCLK, ADCDATA, DACDATA, GPIO4 to GPIO9 Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level 7.10 AUXILIARY ADC Test ...
Page 25
Production Data 8 TYPICAL POWER CONSUMPTION ADC Master Mode 48kHz AVDD HPVDD DBVDD (V) (V) (V) 2.5 2.5 1.71 3.3 3.3 3.3 3.6 3.6 3.6 ADC Master Mode 1kHz Tone 100mVpk-pk AVDD HPVDD DBVDD (V) (V) (V) 2.5 2.5 1.71 ...
Page 26
WM8352 DAC OUT1 Master Mode Pink Noise AVDD HPVDD DBVDD (V) (V) (V) 2.5 2.5 1.71 3.3 3.3 3.3 3.6 5.5 3.6 DAC OUT1 Master Mode 1kHz Tone, 16Ω Load AVDD HPVDD DBVDD (V) (V) (V) 2.5 2.5 1.71 3.3 ...
Page 27
Production Data 9 TYPICAL PERFORMANCE DATA 9.1 AUDIO CODEC Typical THD+N performance of the Headphone Drivers is shown below for 16Ω and 32Ω headphone loads. These graphs are derived whilst using the WM8352 Power Management to generate the power supply ...
Page 28
WM8352 9.2 DC-DC CONVERTERS 9.2.1 EFFICIENCY vs LOAD DCDC1 100 STANDBY 0.001 0.01 LOAD (A) Figure 1 DC-DC1 ...
Page 29
Production Data EFFICIENCY vs LOAD DCDC2 100 3. 3. 0.001 0.01 LOAD (A) Figure 5 DC-DC2 Efficiency Vs Load Current Vo=5V 9.2 ...
Page 30
WM8352 9.2.3 V OUT V = 5.0V 1.2V, Load = 0.05A (Standby Max) IN OUT I OUT LX Figure 8 DC-DC1 STANDBY to ACTIVE Handover at Maximum Standby Current w DYNAMIC OUTPUT VOLTAGE V = 5.0V ...
Page 31
Production Data 9.3 LDO REGULATORS LDO1 LOAD REGULATION 3.09 3.08 3.07 3.06 3.05 3.04 3.03 3.02 3. 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 IOUT (A) Figure 10 LDO1 Output Voltage Versus Output Current 140.0 120.0 100.0 ...
Page 32
WM8352 10 SIGNAL TIMING REQUIREMENTS 10.1 SYSTEM CLOCK TIMING Figure 14 Master Clock Timing Master Clock Timing PARAMETER SYMBOL MCLK cycle time MCLK duty cycle 10.2 AUDIO INTERFACE TIMING - MASTER MODE Figure 15 Digital Audio Data Timing – Master ...
Page 33
Production Data 10.3 AUDIO INTERFACE TIMING - SLAVE MODE Figure 16 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, DGND = 0V, T PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse ...
Page 34
WM8352 10.4 AUDIO INTERFACE TIMING - TDM MODE In TDM mode important that two ADC devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8352 ADCDAT tri-stating at the start and end of ...
Page 35
Production Data 10.5 CONTROL INTERFACE TIMING Figure 18 Control Interface Timing - 2-wire Control Mode Test Conditions DCVDD = 1.8V, DBVDD = 3.3V, DGND = 0V, T PARAMETER SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) ...
Page 36
WM8352 Figure 19 Control Interface Timing - 3-wire Control Mode (Write Cycle) Figure 20 Control Interface Timing - 3-wire Control Mode (Read Cycle) Test Conditions DBVDD = 3.3V, DGND = 0V +25 A PARAMETER CSB falling edge to ...
Page 37
Production Data t CSU CSB input (GPIO7) SCLK (input) SDATA (input) Figure 21 Control Interface Timing - 4-wire Control Mode (Write Cycle) CSB input (GPIO7) SCLK (input) SDOUT output (GPIO6) Figure 22 Control Interface Timing - 4-wire Control Mode (Read ...
Page 38
WM8352 11 CONTROL INTERFACE 11.1 GENERAL DESCRIPTION The WM8352 is controlled by writing to its control registers. Readback is available for most registers. Most aspects of the WM8352 operation can be controlled via this interface. The control interface can operate ...
Page 39
Production Data 11.3 2-WIRE SERIAL CONTROL MODE The 2-wire control interface normally uses the SCLK and SDATA pins, which are referenced to the digital buffer supply, DBVDD. (In Development mode, the interface is initially redirected, with GPIO10 and GPIO11 effectively ...
Page 40
WM8352 The sequence of signals associated with a single register write operation is illustrated in Figure 23. Figure 23 Control Interface 2-wire Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 24. ...
Page 41
Production Data Figure 27 Multiple Register Write to Specified Address using Auto-increment Figure 28 Multiple Register Read from Specified Address using Auto-increment Figure 29 Multiple Register Read from Last Address using Auto-increment Multiple Write and Multiple Read operations enable the ...
Page 42
WM8352 11.4 3-WIRE SERIAL CONTROL MODE The 3-wire control interface uses the CSB, SCLK and SDATA pins, which are referenced to the digital buffer supply, DBVDD. (In 3-wire mode, CSB is provided on GPIO7.) 3-wire control mode is selected by ...
Page 43
Production Data 11.5 4-WIRE SERIAL CONTROL MODE The 4-wire control interface uses the CSB, SCLK, SDATA and SDOUT pins, which are referenced to the digital buffer supply, DBVDD. (In 4-wire mode, SDOUT is provided on GPIO6; CSB is provided on ...
Page 44
WM8352 11.6 REGISTER LOCKING Certain control fields are protected against accidental overwriting. This includes: By default, these registers are locked, i.e. writing to them has no effect. However, they can be unlocked by writing a value of 0013h ...
Page 45
Production Data 12 CLOCKING, TIMING AND SAMPLE RATES 12.1 GENERAL DESCRIPTION The WM8352 includes clocking circuitry for the on-chip audio CODEC, the DC-DC converters and the auxiliary ADC. It provides the following capabilities: The WM8352 has two internal clock generators: ...
Page 46
WM8352 12.1.1 The WM8352 audio CODEC core requires an accurate, low-jitter clock. Clocks for the ADCs, DACs, DSP core functions, and the digital audio interface are all derived from a common internal clock source, SYSCLK. This clock may be derived ...
Page 47
Production Data The oscillator is enabled by the OSC32K_ENA field, as described in Table enabled by default and remains enabled when the WM8352 is in the OFF or BACKUP state. ADDRESS R12 (0Ch) Power Mgmt (5) R218 ...
Page 48
WM8352 When the GPIO5 pin is configured as CODEC_OPCLK, a clock derived from SYSCLK may be output on this pin to provide clocking for other parts of the system. The frequency of this signal is set by OPCLK_DIV. Alternate GPIO ...
Page 49
Production Data 12.3.1 The MCLK_SEL bit is used to select the source for SYSCLK. The source may be either directly from the MCLK input or may be from the output of the FLL. If required, the selected source may be ...
Page 50
WM8352 12.3.2 The ADC and DAC sample rates are independently selectable, relative to SYSCLK, by setting the register fields ADC_CLKDIV and DAC_CLKDIV. These fields must be set according to the SYSCLK frequency, and according to the selected mode of operation ...
Page 51
Production Data SYSCLK 12.2880 MHz 11.2896 MHz 12.0000 MHz 2.0480 MHz Table 10 Derivation of Sample Rates in Normal / USB Modes Note that, in USB mode, the ADC / DAC sample rates do not match exactly with the commonly ...
Page 52
WM8352 12.3.3 In Master Mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV, as described in Table 11. BCLK_DIV must be set to an appropriate value to ensure that there are sufficient BCLK cycles to transfer ...
Page 53
Production Data Table 12 shows the maximum word lengths supported for a given SYSCLK and BCLK_DIV, assuming that one or both the ADCs and DACs are running at maximum rate. SYSCLK 12.288 MHz 11.2896 MHz Table 12 BCLK Divider in ...
Page 54
WM8352 12.3.4 In Master Mode, ADCLRCLK and DACLRCLK are derived from BCLK via programmable dividers set by ADCLRC_RATE and DACLRC_RATE. The BCLK frequency is derived from SYSCLK according to BCLK_DIV, as described earlier in Table 11. In Slave Mode, ADCLRCLK ...
Page 55
Production Data 12.3.5 When the GPIO5 pin is configured as CODEC_OPCLK, a clock derived from SYSCLK may be output on this pin to provide clocking for other parts of the system. The frequency of this signal is derived from SYSCLK ...
Page 56
WM8352 The field FLL_RATE controls internal functions within the FLL recommended that only the default setting be used for this parameter. FLL_RSP_RATE controls the internal loop gain and should be set to the recommended value. The FLL output ...
Page 57
Production Data REGISTER ADDRESS R43 (2Bh) FLL Control 2 R44 (2Ch) FLL Control 3 R45 (2Dh) FLL Control 4 Table 17 FLL Control Registers w BIT LABEL DEFAULT FLL_RSP_RAT 7:4 0000 E FLL_RATE 2:0 000 [2:0] 15:11 FLL_RATIO 14 [4:0] ...
Page 58
WM8352 12.4.1 To generate 12.288 MHz output (F Note that, for best performance, FLL Fractional Mode should always be used. If the calculations yield an integer value of N.K, then it is ...
Page 59
Production Data 12.4.2 Table 18 provides example FLL settings for generating common SYSCLK frequencies from a variety of low and high frequency reference inputs REF OUT VCO 32.000 12.288 98.304 kHz MHz MHz 32.000 11.2896 90.3168 kHz ...
Page 60
WM8352 13 AUDIO CODEC SUBSYSTEM 13.1 GENERAL DESCRIPTION The WM8352 includes a high-performance stereo CODEC. Analogue output buffers and input amplifiers are integrated on-chip, enabling the WM8352 to connect directly to headphones and microphones as well as line-in and line-out ...
Page 61
Production Data 13.2 AUDIO PATHS Figure 36 WM8352 Audio Path Diagram w WM8352 PD, March 2010, Rev 4.2 61 ...
Page 62
WM8352 13.3 ENABLING THE AUDIO CODEC Before the audio CODEC can be used, it must be enabled by writing to the CODEC_ENA, SYSCLK_ENA and BIAS_ENA register bits. ADDRESS R12 (0Ch) Power Mgmt 5 R11 (0Bh) Power Mgmt 4 R8 (08h) ...
Page 63
Production Data Power Down: 1. Mute all outputs 2. Enable anti-pop circuits by setting ANTI_POP = 01. 3. Disable circuits down-stream on outputs 4. Disable VMID by setting VMID_ENA = 0. 5. Wait for VMID to discharge (typically 500ms) 6. ...
Page 64
WM8352 13.4 INPUT SIGNAL PATH The WM8352 has multiple analogue inputs. There are two input channels, Left and Right, each of which consists of an input PGA stage followed by a boost/mix stage switch into the hi-fi ADC. Each input ...
Page 65
Production Data 13.4.2 ADDRESS R9 (09h) Power Mgmt 2 R80 (50h) Left Input Volume R81 (51h) Right Input Volume Note: These bits can be accessed through R9 or through R80/R81. Reading from or writing to either register location has the ...
Page 66
WM8352 13.4.4 The gain of each microphone pre-amplifier is controlled by writing to the appropriate control registers. The gain of each pre-amplifier applies to all three inputs associated with that pre-amplifier, whether inverting or non-inverting. Although the gain settings for ...
Page 67
Production Data 13.4.5 The WM8352 provides a programmable, low-noise bias voltage for condenser electret microphones on the MICBIAS pin. ADDRESS R8 (08h) Power Mgmt 1 R74 (4Ah) Mic Bias Control Note: MICB_ENA can be accessed through R8 or through R74. ...
Page 68
WM8352 REGISTER ADDRESS R9 (09h) Power Mgmt 2 R73 (49h) IN3 Input Control Note: IN3L_ENA and IN3R_ENA can be accessed through R9 or through R73. Reading from or writing to either register location has the same effect. Table 24 Controlling ...
Page 69
Production Data 13.4.7 The WM8352 has mixers in the input signal paths. This allows each ADC to record either a single input signal or a mix of several signals, as desired. The gain for the different input signals can also ...
Page 70
WM8352 ADDRESS R9 (09h) Power Mgmt 2 R98 (62h) Input mixer volume for left channel R99 (63h) Input mixer volume for right channel R100 (64h) OUT4 Mixer Control Table 25 Input Mixer Control w BIT LABEL DEFAULT 7 MIXINR_ENA 0 ...
Page 71
Production Data 13.5 ANALOGUE TO DIGITAL CONVERTER (ADC) The high-performance stereo ADC within the WM8352 converts analogue input signals to the digital domain. It uses a multi-bit, over-sampled sigma-delta architecture. The ADC’s over-sampling rate is selectable to control the trade-off ...
Page 72
WM8352 13.5.1 Programmable digital volume control is provided to attenuate the ADC’s output signal. ADDRESS R66 (42h) ADC Digital Volume L R67 (43h) ADC Digital Volume R Table 27 ADC Volume Control 13.5.2 A digital high-pass filter is provided to ...
Page 73
Production Data 13.6 DIGITAL MIXING 13.6.1 A digital sidetone is available when ADCs and DACs are operating at the same sample rate. Digital data from either left or right ADC can be mixed with the audio interface data on the ...
Page 74
WM8352 ADCL_DAC_SVOL or ADCR_DAC_SVOL Table 30 Digital Side Tone Control w SIDETONE VOLUME 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 1101 ...
Page 75
Production Data 13.7 DIGITAL TO ANALOGUE CONVERTER (DAC) The WM8352 contains a high-performance stereo DAC to convert digital audio signals to the analogue domain. Audio data is passed to the WM8352 via the audio interface, and passes through a variety ...
Page 76
WM8352 13.7.1 REGISTER ADDRESS R50 (32h) DAC Digital Volume Left R51 (33h) DAC Digital Volume Right Table 32 DAC Volume Control 13.7.2 The WM8352 has a soft mute function which, when enabled, gradually attenuates the volume of the DAC output. ...
Page 77
Production Data The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit. Ramp rates of fs/32 and fs/2 are selectable as shown REGISTER ADDRESS R58 (3Ah) DAC Mute R59 (3Bh) DAC Mute Volume Table 33 ...
Page 78
WM8352 13.7.4 The digital audio data is converted to oversampled bit streams in the on-chip 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The multi-bit DAC architecture ...
Page 79
Production Data 13.8 OUTPUT SIGNAL PATH The analogue output pins produce audio signals to drive headphones, line-out connections and/or external loudspeaker amplifiers. These pins include: OUT1L, OUT1R, OUT2L and OUT2R have individual analogue volume PGAs with -57dB ...
Page 80
WM8352 13.8.2 The left and right output channel mixers are shown in Figure 43. These mixers allow the AUX inputs, the ADC bypass and the DAC left and right channels to be combined as desired. This allows a mono mix ...
Page 81
Production Data Each output mixer can be enabled or disabled by writing either to the power management control register or to the respective mixer’s own control register. Each analogue signal going into the output mixers can be independently enabled or ...
Page 82
WM8352 The gain for microphone pre-amp and auxiliary input (IN3L/IN3R) signals can be independently adjusted for each output mixer. This does not affect the volume of the same signals going into the separate record mixer. The level of the DAC ...
Page 83
Production Data 13.9 ANALOGUE OUTPUTS 13.9.1 The headphone outputs, OUT1L and OUT1R can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors coupled without any capacitor. Each output has an analogue volume control PGA with ...
Page 84
WM8352 ADDRESS R104 (68h) OUT1L Volume R105 (69h) OUT1R Volume R76 (4Ch) Output Control Table 40 Controlling OUT1L and OUT1R w BIT LABEL DEFAULT OUT1L_MUTE OUT1L_ZC 0 8 OUT1_VU 0 7:2 OUT1L_VOL 11_1001 [5:0] 14 OUT1R_MUTE 0 ...
Page 85
Production Data 13.9.2 OUT2L and OUT2R are designed as a stereo pair and can drive a headphone, a line load or a loudspeaker amplifier. Each output has an analogue volume control PGA with a gain range of -57dB to +6dB ...
Page 86
WM8352 ADDRESS R106 (6Ah) for OUT2L Volume R107 (6Bh) for OUT2R R76 (4Ch) Output Control Table 41 Controlling OUT2L and OUT2R w BIT LABEL DEFAULT OUT2L_MU OUT2L mute normal operation 1 = mute 13 OUT2L_ZC ...
Page 87
Production Data A beep signal on the IN3R pin (see Table 42) can be mixed into OUT2R independently of the right output mixer (i.e. without mixing the same beep signal into OUT1R). ADDRESS R111 (6Fh) Beep Volume Table 42 Controlling ...
Page 88
WM8352 Notes: The above figures illustrate the headphone connections to outputs OUT1L and OUT1R. The equivalent configurations apply equally to OUT2L and OUT2R. The DC-coupled configuration illustrated in Figure 47 shows OUT4 (muted) being used as the Ground Return connection. ...
Page 89
Production Data 13.9.4 The additional analogue outputs OUT3 and OUT4 have independent mixers and can be used in a number of different ways: The OUT3 and OUT4 output stages are powered from HPVDD and HPGND. If OUT4 ...
Page 90
WM8352 OUT3 can provide a buffered midrail headphone pseudo-ground left line output. It can also be a common mode input for OUT2L/OUT2R. OUT4 can provide a buffered midrail headphone pseudo- ground, a right line output mono ...
Page 91
Production Data 13.10 DIGITAL AUDIO INTERFACE The audio interface enables the WM8352 to exchange audio data with other system components separate from the control interface and has four dedicated pins: The LRCLK and BCLK ...
Page 92
WM8352 ADDRESS R114 (72h) Audio Interface ADC Control R115 (73h) Audio Interface DAC Control Table 45 Selecting the Audio Data Format In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK transition. ...
Page 93
Production Data In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may ...
Page 94
WM8352 Figure 54 DSP/PCM Mode Audio Interface (mode B, AIF_LRCLK_INV=1) 13.10.2 AUDIO INTERFACE TDM MODE The digital audio interface on WM8352 has the facility of tri-stating the ADCDAT pin to allow multiple data sources to operate on the same bus. ...
Page 95
Production Data Figure 56 Right Justified Mode with TDM I2S Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 to the start of SLOT1 is determined by the selected word ...
Page 96
WM8352 Figure 59 DSP/PCM Mode B, Master Mode, with TDM DSP/PCM Mode A, Slave Mode: SLOT0 and SLOT1 are defined as shown below. The number of BCLK cycles from the start of SLOT0 (left) to the start of SLOT1 (left) ...
Page 97
Production Data 13.11 COMPANDING The WM8352 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to the DAC_COMP or ADC_COMP ...
Page 98
WM8352 120 100 Figure 39 μ-Law Companding 120 100 Figure 40 A-Law Companding w u-law Companding 0.1 0.2 0.3 0.4 Normalised Input A-law Companding 0 0 0.2 0.4 Normalised Input ...
Page 99
Production Data 13.12 ADDITIONAL CODEC FUNCTIONS 13.12.1 HEADPHONE JACK DETECT The IN2L and IN2R pins can be selected as headphone jack detect inputs, to enable automatic control of the analogue outputs when a headphone is plugged into a jack socket. ...
Page 100
WM8352 13.12.2 MICROPHONE DETECTION The WM8352 can detect when a microphone has been plugged in, and/or when the microphone is short-circuited. It detects these events by comparing the current drawn from the MICBIAS pin against two thresholds. The thresholds for ...
Page 101
Production Data 13.12.3 MID-RAIL REFERENCE (VMID) VMID provides a potential mid-way between AVDD and GND, used in many parts of the audio CODEC generated from AVDD using on-chip potential dividers. Different resistor values can be selected for this ...
Page 102
WM8352 13.12.4 ANTI-POP CONTROL ADDRESS R78 (4Eh) Anti pop control Table 50 Control Registers for Anti-pop w BIT LABEL DEFAULT 9:8 ANTI_POP [1:0] 00 DIS_OP_LN4 [1:0] 7:6 00 5:4 DIS_OP_LN3 [1:0] 00 3:2 DIS_OP_OUT2 [1:0] 00 1:0 DIS_OP_OUT1 [1:0] 00 ...
Page 103
Production Data 13.12.5 UNUSED ANALOGUE INPUTS/OUTPUTS Whenever an analogue input/output is disabled, it remains connected to AVDD/2 through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between the voltage buffer and the output ...
Page 104
WM8352 AVDD/2 AVDD/2 Figure 63 Unused Input/Output Pin Tie-off Buffers OUT1R/L_ENA/ OUT2R/L_ENA OUT3/4_ENA Table 52 Unused Output Pin Tie-off Options w - AVDD/2 + VBUF_ENA R8[13] Used to tie off all unused inputs. OUT1L_ENA R10[0] OUT1R_ENA - AVDD/2 R10[1] + ...
Page 105
Production Data 13.12.6 ZERO CROSS TIMEOUT A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output PGAs the gain will automatically update after a timeout period if a zero cross has ...
Page 106
WM8352 14 POWER MANAGEMENT SUBSYSTEM 14.1 GENERAL DESCRIPTION The WM8352 provides 6 DC-DC Converters and 4 LDO Regulators which each deliver high efficiency across a wide range of line and load conditions. These power management components are designed to support ...
Page 107
Production Data Figure 64 WM8352 Operating State Diagram 14.2.1 The WM8352 moves from the ACTIVE to the HIBERNATE state when the HIBERNATE register bit is set. It can also move to hibernate using the Hibernate Edge or the Hibernate Level ...
Page 108
WM8352 14.3 POWER SEQUENCING AND CONTROL 14.3.1 The WM8352 moves from OFF or HIBERNATE states to the ACTIVE state when a startup event occurs. Startup events include: The start-up events are only valid provided ...
Page 109
Production Data ADDRESS R39 (27h) Comparator Interrupt Status Mask Table 55 Wake-Up Interrupts 14.3.2 The WM8352 power supply blocks can be commanded to start up according to a defined sequence when the WM8352 is commanded into the ACTIVE state. This ...
Page 110
WM8352 ADDRESS R3 (03h) System Control 1 Table 56 Software Shutdown As part of the shutdown sequence, the WM8352 asserts the /RST and /MEMRST reset signals, resets its internal control registers, disables most of its functions, resets the CHIP_ON bit ...
Page 111
Production Data 14.3.6 The WM8352 provides an active-low reset output signal to the host processor on the open-drain /RST pin. The /RST pin is asserted low in the OFF state. The status of the /RST pin in HIBERNATE state is ...
Page 112
WM8352 happen before the I2C Acknowledge has been clocked by the host processor. If the /RST signal causes the processor to reset before it has clocked the I2C Acknowledge, then the WM8352 will continue to assert the Acknowledge signal (ie. ...
Page 113
Production Data ADDRESS R6 (06h) Interface Control Note: In custom modes (CONF[1:0]≠00), the secondary control interface is never used and the control bits described here have no effect. Table 61 Control Interface Switching in Development Mode 14.4.2 In Development mode, ...
Page 114
WM8352 By default, the DO_CONF output will be set low when the WM8352 enters the OFF state and set high on every transition from OFF to ACTIVE, re-triggering the external ‘genie’. Also, by default, the internal control registers will be ...
Page 115
Production Data 14.4.3 The WM8352 can be configured in Development mode by writing to control bits that determine its startup behaviour. The locations of these register bits are shown in Table 63 below. A typical configuration sequence would include writes ...
Page 116
WM8352 REGISTER Select /RST duration R3 (03h) Unlock protected registers R219 (DBh) Alternate function and input/output selection for GPIO pins R140 (8Ch) GP3_FN R141 (8Dh) GP7_FN R142 (8Eh) GP11_FN R143 (8Fh) R128 (80h) GPn_DB (n = ...
Page 117
Production Data 14.5 CUSTOM MODES The WM8352 provides three custom start-up modes. These are selected by setting the CONF1 and CONF0 pins = 01 11. The custom mode start-up sequences define the following parameters: ...
Page 118
WM8352 SUPPLY DCDC1 DCDC2 DCDC3 DCDC4 DCDC5 DCDC6 LDO1 LDO2 LDO3 LDO4 Table 64 Default Supply Voltages / Power-up Sequence for Configuration Mode 01 Figure 66 Power-up Sequence - Configuration Mode 01 w REGISTER SETTING DC1_ENSLOT [3:0] = 0001 DC1_VSEL ...
Page 119
Production Data The default GPIO settings for configuration mode 01 are shown below in Table 65. GPIO PIN POWER DOMAIN GPIO0 VRTC GP0_FN [3:0] = 0000 GPIO1 VRTC GP1_FN [3:0] = 0000 GPIO2 VRTC GP2_FN [3:0] = 0011 GPIO3 VRTC ...
Page 120
WM8352 14.5.2 In Configuration Mode 10, the following general default settings apply: PARAMETER ON polarity USB power source Watchdog timer Control Interface 32kHz oscillator Real Time Clock LDO1 Crystal detect mode The default voltages and the power-up sequence for all ...
Page 121
Production Data SUPPLY DCDC1 DCDC2 DCDC3 DCDC4 DCDC5 DCDC6 LDO1 LDO2 LDO3 LDO4 Table 66 Default Supply Voltages / Power-up Sequence for Configuration Mode 10 Figure 67 Power-up Sequence - Configuration Mode 10 w REGISTER SETTING DC1_ENSLOT [3:0] = 0010 ...
Page 122
WM8352 The default GPIO settings for configuration mode 10 are shown below in Table 67. GPIO PIN POWER DOMAIN GPIO0 VRTC GP0_FN [3:0] = 0000 GPIO1 VRTC GP1_FN [3:0] = 0001 GPIO2 VRTC GP2_FN [3:0] = 0011 GPIO3 VRTC GP3_FN ...
Page 123
Production Data 14.5.3 In Configuration Mode 11, the following general default settings apply: PARAMETER ON polarity USB power source Watchdog timer Control Interface 32kHz oscillator Real Time Clock LDO1 Crystal detect mode The default voltages and the power-up sequence for ...
Page 124
WM8352 SUPPLY DCDC1 DCDC2 DCDC3 DCDC4 DCDC5 DCDC6 LDO1 LDO2 LDO3 LDO4 Table 68 Default Supply Voltages / Power-up Sequence for Configuration Mode 11 Figure 68 Power-up Sequence - Configuration Mode 11 w REGISTER SETTING DC1_ENSLOT [3:0] = 0001 DC1_VSEL ...
Page 125
Production Data The default GPIO settings for configuration mode 11 are shown below in Table 69. GPIO PIN POWER DOMAIN GPIO0 VRTC GP0_FN [3:0] = 0000 GPIO1 VRTC GP1_FN [3:0] = 0001 GPIO2 VRTC GP2_FN [3:0] = 0011 GPIO3 VRTC ...
Page 126
WM8352 14.6 CONFIGURING THE DC-DC CONVERTERS The configuration of the DC-DC converters is described in the following sections. Some of the control fields form part of the Custom Mode configuration settings and therefore will not require to be set in ...
Page 127
Production Data 14.6.2 The DC-DC converters are controlled by an internally generated clock signal from the RC Oscillator with a constant frequency of around 2.0MHz for DC- and 6, and a constant frequency of around 1.0MHz for ...
Page 128
WM8352 DC-DC Converters and 6 can also be controlled by the device HIBERNATE bit hardware input signals L_PWR1, L_PWR2 and L_PWR3. Several GPIO pins can be assigned as L_PWR pins. Each converter can be assigned ...
Page 129
Production Data The default output voltage for DC-DC Converters and 6 is set by writing to the DCn_VSEL register bits. The ‘image’ voltage settings DCn_VIMG are alternate values that may be invoked when the HIBERNATE software or ...
Page 130
WM8352 A summary of the Mode Control and Voltage Control for DC-DC Converter 1 is provided in Table 75. Note that “Hibernate” in Table 75 refers to a GPIO Hibernate input or to the applicable Hibernate signal selected by the ...
Page 131
Production Data In all configurations, the input pins VP2 and VP5 must be externally wired to one of the supply rails, BATT or LINE. Using LINE has the advantage that the converters can operate when the battery is flat, defective ...
Page 132
WM8352 ADDRESS R183 (B7h) for DC-DC2 R192 (C0h) for DC-DC5 Note either and identifies the individual DC-DC converter Table 77 Hibernate Mode Control for DC-DC Converters 2 and 5 14.6.5 Each DC-DC Converter is monitored ...
Page 133
Production Data The DC-DC Converters and the LDO Regulators have a first-level interrupt, UV_INT (see Section 24). This comprises second-level interrupts from each of the DC-DC Converters and the LDO Regulators. Each DC-DC Converter has a dedicated second-level interrupt which ...
Page 134
WM8352 The status of the DC-DC Converters can be indicated and monitored externally via a GPIO pin configured as /VCC_FAULT (see Section 20). When a GPIO pin is configured as /VCC_FAULT output, a logic low level on this pin indicates ...
Page 135
Production Data 14.7 CONFIGURING THE LDO REGULATORS The configuration of the LDO Regulators is described in the following sections. Some of the control fields form part of the Custom Mode configuration settings and therefore will not require to be set ...
Page 136
WM8352 ADDRESS R201 (C9h) for LDO1 R204 (CCh) for LDO2 R207 (CFh) for LDO3 R210 (D2h) for LDO4 Note number between 1 and 4 that identifies the individual DC-DC converter Table 81 Enabling and Disabling the LDO ...
Page 137
Production Data The LDO Regulators can also be controlled by the device HIBERNATE bit hardware input signals L_PWR1, L_PWR2 and L_PWR3. Several GPIO pins can be assigned as L_PWR pins. Each Regulator can be assigned to one of ...
Page 138
WM8352 14.7.3 Each LDO Regulator is monitored for voltage accuracy and fault conditions. An undervoltage condition is set if the voltage falls below 95% of the required level. The action taken in response to a fault condition can be set ...
Page 139
Production Data The status of the LDO Regulators can be indicated and monitored externally via a GPIO pin configured as /VCC_FAULT (see Section 20). When a GPIO pin is configured as /VCC_FAULT output, a logic low level on this pin ...
Page 140
WM8352 14.8 DC-DC CONVERTER OPERATION 14.8.1 The WM8352 provides six DC-DC switching converters. Four of these are Buck (Step-down) converters and two are Boost (Step-up) converters. The principal characteristics and typical usage for each DC-DC converter are shown below. Typical ...
Page 141
Production Data 14.8.2 DC-DC Converters and 6 are versatile step-down, pulse-width-modulated (PWM) DC-DC converters designed to deliver high power efficiency across full load conditions. The converters offer Active and Standby/Hysteretic operating modes in order to maximise efficiency ...
Page 142
WM8352 14.8.3 DC-DC Converters 2 and 5 are versatile step-up pulse-width-modulated (PWM) DC-DC converters designed to deliver high power efficiency across full load conditions. The converters can also be used as switches. DC-DC Converters 2 and 5 are designed with ...
Page 143
Production Data 14.9 LDO REGULATOR OPERATION The WM8352 provides four identical LDO voltage regulators to generate accurate, low-noise supply voltages for various system components. The LDOs can also operate as current-limited switches, with no voltage regulation; this is useful for ...
Page 144
WM8352 15 CURRENT LIMIT SWITCH 15.1 GENERAL DESCRIPTION The WM8352 includes an on-chip Current Limit Switch to control external devices and to support hot- plugging of accessories and power supplies. When the switch is enabled, it normally has a low ...
Page 145
Production Data 15.2.2 The Current Limit Switch can be connected to voltages which may be higher than the device LINE voltage. To support this capability, the switch is powered from the highest available voltage; this requires a bulk detection circuit ...
Page 146
WM8352 The status of the Current Limit Switch can be indicated and monitored externally via a GPIO pin configured as /VCC_FAULT (see Section 20). When a GPIO pin is configured as /VCC_FAULT output, a logic low level on this pin ...
Page 147
Production Data 16 CURRENT SINKS (LED DRIVERS) 16.1 GENERAL DESCRIPTION The WM8352 includes five pins for driving different types of LEDs. The pins ISINKA and ISINKB provide programmable constant-current sinks designed to drive strings of serially connected LEDs, including white ...
Page 148
WM8352 16.2.2 The sink currents for ISINKA and ISINKB can be independently programmed by writing to the CS1_ISEL and CS2_ISEL register bits. The current steps are logarithmic to match the logarithmic light sensitivity characteristic of the human eye. The step ...
Page 149
Production Data ADDRESS R173 (ADh) for ISINKA R175 (AFh) for ISINKB Note either ‘1’ for ISINKA or ‘2’ for ISINKB Table 97 Configuring Flash Mode for ISINKA and ISINKB w BIT LABEL DEFAULT 15 CSn_FLASH_M 0 ODE CSn_TRIGSRC ...
Page 150
WM8352 16.2.4 The sink currents for ISINKA and ISINKB can be programmed to switch on and off gradually in LED and in Flash modes. The current ramp durations are set as described in Table 98. ADDRESS R173 (ADh) for ISINKA ...
Page 151
Production Data 16.3 OPEN-DRAIN LED OUTPUTS The three open-drain outputs ISINKC, ISINKD and ISINKE are alternate functions of the GPIO10, GPIO11 and GPIO12 pins, respectively (see Section 20). They can drive LEDs connected to LINE, with a series resistor. Note ...
Page 152
WM8352 17 POWER SUPPLY CONTROL 17.1 GENERAL DESCRIPTION The WM8352 can take its power supply from a Wall adaptor, a USB interface or from a single-cell lithium battery. The WM8352 autonomously chooses the most appropriate power source available, and supports ...
Page 153
Production Data HIVDD is an external connection which exists for the purposes of decoupling only. It represents the highest available power supply connected to the WM8352. It should be noted that the preferred supply (on the LINE pin) is not ...
Page 154
WM8352 17.4 USB POWERED OPERATION The WM8352 selects USB Slave mode by default. In USB Slave Mode, the USB pin can be used as one of the sources of power for the WM8352. In USB Master Mode (selected using the ...
Page 155
Production Data ADDRESS R4 (04h) System Control 2 Table 100 Selecting USB Power Modes The USB connection has its own first-level interrupt, USB_INT (see Section 24). This contains a single second-level interrupt, USB_LIMIT_EINT, which indicates an over-current condition. USB_LIMIT_EINT can ...
Page 156
WM8352 17.5 EXTERNAL INTERRUPTS The power supply control circuit has a first-level interrupt, EXT_INT (see Section 24). This comprises three second-level interrupts which indicate if the USB, Wall or Battery supplies have been connected or disconnected. Internal feedback signals USB_FB, ...
Page 157
Production Data 17.7 BATTERY CHARGER 17.7.1 The WM8352 incorporates a battery charger which is designed for single-cell lithium batteries. The battery charger can operate from either the Wall (LINE) or USB power sources. Trickle charging at 50mA is enabled by ...
Page 158
WM8352 Fast charging consists of two phases: In the constant current phase, the WM8352 drives a programmable constant current into the battery through the BATT pin. During this phase, the battery voltage rises monotonically until the battery reaches the target ...
Page 159
Production Data 17.7.2 The battery charger is enabled by default when the WM8352 is in the ACTIVE, HIBERNATE or OFF states. Note that battery charging is only possible when the selected power source is within normal operating limits (see Section ...
Page 160
WM8352 If the USB current limit cannot support the charge current demanded by CHG_TRICKLE_SEL and USB current choking is enabled, then the charge current will be modified, where possible, in order to continue charging. The trickle charge current cannot be ...
Page 161
Production Data 17.7.4 Fast charging provides a faster way to charge the battery. This is only possible under certain conditions. Fast charging must be initiated by the system controller, and can never start autonomously. Fast charging is normally possible in ...
Page 162
WM8352 The register control fields for Fast Charging are described in Table 105. See Section 17.7.5 for details of battery charger termination. ADDRESS R25 (15h) Interrupt Status 1 R168 (A8h) Battery charger control 1 R169 (A9h) Battery charger control 2 ...
Page 163
Production Data 17.7.5 Fast charging and Trickle charging is terminated under any of the following conditions: The End of Charge Current threshold can be set between 20mA and 90mA, using the CHG_EOC_SEL register field, as defined in ...
Page 164
WM8352 ADDRESS R169 (A9h) Battery charger control 2 Table 106 Battery Charger Termination 17.7.6 The status of the Battery Charger can be read from the CHG_STS register field, as described in Table 107. This field indicates whether the charger is ...
Page 165
Production Data 17.7.7 The WM8352 continuously monitors battery temperature, chip temperature and battery voltage. In case of a fault condition, it autonomously takes appropriate action, and alerts the host processor via the applicable interrupt flags. Battery Temperature Monitoring The WM8352 ...
Page 166
WM8352 Chip Temperature Monitoring The WM8352 has a built-in temperature sensor to monitor the silicon die temperature. If the chip temperature reaches the thermal warning level, the WM8352 sets the SYS_CHIP_GT115_EINT (see Section 25) and Battery Charger operation may be ...
Page 167
Production Data 17.7.8 The battery charger can raise a first-level interrupt, CHG_INT (see Section 24) to report status and fault conditions to the host processor. The CHG_INT interrupt is the logical OR of all the second-level interrupts described in Table ...
Page 168
WM8352 18 SYSTEM MONITORING AND UNDERVOLTAGE LOCKOUT (UVLO) The WM8352 includes several mechanisms to prevent the system from starting up, or force it to shut down, when power sources are critically low. The under-voltage lockout (UVLO non-programmable voltage ...
Page 169
Production Data ADDRESS R26 (1Ah) Interrupt Status 2 R34 (22h) Interrupt Status 2 Mask Table 112 Battery Monitoring and UVLO Interrupts w BIT LABEL SYS_HYST_COMP_FAIL_ 3 EINT 3 IM_SYS_HYST_COMP_FAI L_EINT WM8352 DESCRIPTION Hysteresis comparator indication that LINE or BATT is ...
Page 170
WM8352 19 AUXILIARY ADC 19.1 GENERAL DESCRIPTION The WM8352 incorporates a low-power 12-bit Auxiliary ADC (AUXADC). This can be used to measure a number of internal or external voltages, with either VREF or VRTC as its reference. A programmable potential ...
Page 171
Production Data 19.2 INITIATING AUXADC MEASUREMENTS The AUXADC can measure voltages on four external pins, AUX1, AUX2, AUX3 and AUX4. It can also measure voltages on the USB, LINE and BATT pins, and also the temperature sensor level. Each of ...
Page 172
WM8352 ADDRESS R145 (91h) Digitiser Control (2) Table 114 Initiating AUXADC Measurements In Polling mode, setting AUXADC_POLL = 1 initiates one set of measurements, after which the AUXADC waits for a new trigger. In Continuous mode, a set of measurements ...
Page 173
Production Data 19.3 VOLTAGE SCALING AND REFERENCES For inputs AUX1, AUX2, AUX3 and AUX4, the AUXADC measurements may be referenced to either VRTC or VREF (see Section 21). The selected reference can be selected independently for each input, using the ...
Page 174
WM8352 19.4 AUXADC READBACK Measured data from the AUXADC can be accessed by reading registers R152 through to R159, as defined in Table 116. This data may be read at any time, or may be read in response to the ...
Page 175
Production Data ADDRESS R152 (98h) AUX1 R153 (99h) AUX2 R154 (9Ah) AUX3 R155 (9Bh) AUX4 R156 (9Ch) USB Voltage Readback R157 (9Dh) LINE Voltage Readback R158 (9Eh) BATT Voltage Readback R159 (9Fh) Chip Temperature Readback R145 (91h) Digitizer Control (2) ...
Page 176
WM8352 19.5 CALIBRATION The on-chip reference VREF provides a highly accurate reference voltage to the AUXADC. For best measurement accuracy, the WM8352 provides a way to determine the voltage offset of the AUXADC’s VREF buffer and the gain error introduced ...
Page 177
Production Data 19.6 DIGITAL COMPARATORS The WM8352 has four digital comparators which may be used to compare AUXADC measurement data against programmable threshold values. Each comparator has an associated interrupt flag, as described in Section 19.7, which indicates that the ...
Page 178
WM8352 19.7 AUXADC INTERRUPTS The AUXADC has five second-level interrupts which can trigger a first-level System Interrupt, AUXADC_INT (see Section 24). These are described in Table 119. Each AUXADC interrupt in Register R26 can be masked by setting the associated ...
Page 179
Production Data 20 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) 20.1 GENERAL DESCRIPTION The WM8352 has thirteen general-purpose input/output (GPIO) pins; GPIO0 - GPIO12. These can be configured as inputs or outputs, active high or active low, with optional on-chip pull-up ...
Page 180
WM8352 20.1.1 To configure a pin as a GPIO, the corresponding GPn_FN register bits must be set to 0000 (see Table 124). Each GPIO pin can be set input output through the corresponding GPn_DIR ...
Page 181
Production Data Note GPIO pin is configured as an open drain output, (ie. GPn_DIR=0, GPn_CFG=1), then the external pull-up voltage must not be greater than the supply domain for the corresponding GPIO. For example, if the GPIO supply ...
Page 182
WM8352 20.2 GPIO ALTERNATE FUNCTIONS 20.2.1 The following alternate functions are available. ALTERNATE FUNCTION NAME ADCLRCLK ADCBCLK CHIP_RESET CSB FLASH HIBERNATE (Level) HIBERNATE (Edge) HEARTBEAT /LDO_ENA L_PWR1 L_PWR2 L_PWR3 MASK /MR PWR_OFF PWR_ON w LIST OF ALTERNATE FUNCTIONS INPUT / ...
Page 183
Production Data ALTERNATE FUNCTION NAME /WAKEUP 32kHz ADA ADCLRCLK ADCLRCLKB ADCBCLK /BATT_FAULT CH_IND CODEC_OPCLK DO_CONF FLASH_OUT FLL_CLK ISINKC ISINKD ISINKE LINE_SW LINE_GT_BATT MICDET MICSHT w INPUT / DESCRIPTION OUTPUT Input Logic input signal causes wakeup from OFF or HIBERNATE states. ...
Page 184
WM8352 ALTERNATE FUNCTION NAME /MEMRST P_CLK POR_B PWR_ON /RST RTC SDOUT /VCC_FAULT VRTC 32kHz Table 123 List of GPIO Alternate Functions 20.2.2 The function of each GPIO pin is programmable by writing to the respective GPn register bits. GPn_FN = ...
Page 185
Production Data ADDRESS R140 (8Ch GPIO function select 1 R141 (8Dh) GPIO function select 2 R142 (8Eh) GPIO function select 3 R143 (8Fh) Table 124 Control Registers to Select GPIO Alternate Functions ADDRESS R140 (8Ch GPIO function select 1 Note: ...
Page 186
WM8352 ADDRESS R141(8Dh) GPIO function select 2 Note: Undocumented combinations for GPn_FN ( are reserved Table 126 GPIO Function Select 2 w BIT LABEL DEFAULT 3:0 GP4_FN Dependant on [3:0] CONFIG settings 7:4 GP5_FN Dependant on ...
Page 187
Production Data ADDRESS R142 (8Eh) GPIO function select 3 Note: Undocumented combinations for GPn_FN ( 11) are reserved Table 127 GPIO Function Select 3 ADDRESS R143 (8Fh) GPIO function select 4 Note: Undocumented combinations are reserved Table ...
Page 188
WM8352 21 VOLTAGE REFERENCES The WM8352 generates several reference voltages used for different purposes. The main reference voltage VREF, and additional internal references derived from it, are used in the DC-DC converters, the LDO regulators and the auxiliary ADC. VREF ...
Page 189
Production Data 22 REAL-TIME CLOCK (RTC) 22.1 GENERAL DESCRIPTION The WM8352 contains a Real Time Clock (RTC), which maintains the current date and time, and also has the capability to generate alarms and periodic interrupt signals. The RTC is powered ...
Page 190
WM8352 The current time can be read from the registers defined above. As the content of the time registers changes every second, a single register read, executed at an arbitrary time, does not guarantee an accurate time reading. Two possible ...
Page 191
Production Data ADDRESS R20 (14h) ALARM sec / min R21 (15h) ALARM hour / day R22 (16h) ALARM date Table 132 RTC Alarm Registers The “don’t care” option (all bits set to 1) provides extra flexibility for programming ALARM duration ...
Page 192
WM8352 22.2.5 Writing to the RTC Alarm registers requires a procedure similar to that used when setting RTC time, in order to prevent accidental alarms being triggered: The RTC_ALMSET and RTC_ALMSTS bits are defined in Table ...
Page 193
Production Data The applicable register bits are defined in Table 134. ADDRESS R12 (0Ch) Power Mgmt (5) R218 (DAh) RTC Tick Control Note: RTC_TICK_ENA can be accessed through R12 or through R218. Reading from or writing to either register location ...
Page 194
WM8352 22.4 RTC GPIO OUTPUT It is possible to configure GPIO6 as an RTC output, as described in Section 20. This output is a square wave that is derived from the trimmed RTC counter. The frequency can be set to ...
Page 195
Production Data 22.5 RTC INTERRUPTS The RTC has its own first-level interrupt, RTC_INT (see Section 24). This comprises three second- level interrupts which indicate periodic events or RTC Alarm conditions. The RTC raises an RTC_SEC_EINT interrupt on every 1 second ...
Page 196
WM8352 23 WATCHDOG TIMER The WM8352 includes a watchdog timer designed to detect a possible software fault condition where the host processor has locked up. The watchdog timer checks for any write operation to the watchdog control register R4 (04h) ...
Page 197
Production Data ADDRESS R26 (1Ah) Interrupt Status 2 R34 (22h) Interrupt Status 2 Mask Table 139 Watchdog Timer Interrupts Note that, if GPIO9 is configured as VCC_FAULT output (GP9_FN = 0001, GP9_DIR = 0), then the Watchdog Timer will be ...
Page 198
WM8352 24 INTERRUPT CONTROLLER The WM8352 can send an interrupt signal to the host processor though the IRQ pin. Interrupts can alert the host to a wide range of events and fault conditions. Each of these can be individually enabled ...
Page 199
Production Data 24.2 FIRST-LEVEL INTERRUPTS Each first level interrupt has a status bit in Register R24, which can be read to determine the origin of an IRQ event. Each of these bits may be masked by setting the corresponding field ...
Page 200
WM8352 24.3 SECOND-LEVEL INTERRUPTS The following sections define the second-level interrupt status and control bits associated with each of the first-level bits defined in Table 141. 24.3.1 The first-level OC_INT interrupt comprises one second-level interrupt for the limit switch. This ...