WM8352GEB/V Wolfson Microelectronics, WM8352GEB/V Datasheet - Page 244

• Manufacturer Part Number: WM8352GEB/V
• Description: Audio CODECs Audio CODEC plus pwr management
• Manufacturer: Wolfson Microelectronics

Specifications of WM8352GEB/V

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, 4-Wire)
• Resolution: 12 bit
• Operating Supply Voltage: 3.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA
• Minimum Operating Temperature: - 25 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 260 uA
• Thd Plus Noise: - 83 dB
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 8
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 95dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8352
Register 29h Clock Control 2
Register 2Ah FLL Control 1
w
REGISTER
REGISTER
ADDRESS
ADDRESS
FLL Control
R42 (2Ah)
R41 (29h)
Control 2
Clock
1
BIT
BIT
10:8
7:4
2:0
15
15
14
0
FLL_RSP_RATE
LRC_ADC_SEL
FLL_RATE [2:0]
FLL_OSC_ENA
FLL_OUTDIV
MCLK_DIR
LABEL
FLL_ENA
LABEL
[2:0]
DEFAULT
DEFAULT
0000
010
000
0
0
0
0
Selects either ADCLRCLK or DACLRCLK to drive
LRCLK pin in Master mode
0 = DACLRCLK
1 = ADCLRCLK
Whether MCLK is an input or an output.
0 = MCLK is an input
1 = MCLK is an output
Digital Enable for FLL
0 = disabled
1 = enabled
Note that FLL_OSC_ENA must be enabled before
enabling FLL_ENA.
Analogue Enable for FLL
0 = FLL disabled
1 = FLL enabled
Note that FLL_OSC_ENA must be enabled before
enabling FLL_ENA.
F
000 = F
001 = F
010 = F
011 = F
100 = F
101 = Reserved
110 = Reserved
111 = Reserved
FLL Loop Gain
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that these are not changed from
default.
Frequency of the FLL control block
000 = F
001 = F
010 = F
011 = F
100 = F
101 = F
Recommended that these are not changed from
default.
OUT
clock divider
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
VCO
/ 2
/ 4
/ 8
/ 16
/ 32
/ 1 (Recommended value)
/ 2
/ 4
/ 8
/ 16
/ 32
DESCRIPTION
DESCRIPTION
PD, March 2010, Rev 4.2
REFER TO
REFER TO
Production Data
244