USB3290-FH-TR SMSC, USB3290-FH-TR Datasheet - Page 27

• Manufacturer Part Number: USB3290-FH-TR
• Description: Telecom Line Management ICs USB 2.0 PHY UTMI
• Manufacturer: SMSC

Specifications of USB3290-FH-TR

• Product: PHY
• Data Rate: 480 Mbps
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface
Datasheet
SMSC USB3290
7.6.3
7.7
7.8
7.8.1
7.8.2
7.8.3
Crystal Oscillator and PLL
Internal Regulators and POR
Bias Generator
This block consists of an internal bandgap reference circuit used for generating the high speed driver
currents and the biasing of the analog circuits. This block requires an external 12k Ω , 1% tolerance,
external reference resistor connected from RBIAS to ground.
The USB3290 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference
clock that is used by the PHY during both transmit and receive. The USB3290 requires a clean 24MHz
crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY
may not operate correctly.
The USB3290 can use either a crystal or an external clock oscillator for the 24MHz reference. The
crystal is connected to the XI and XO pins as shown in the application diagram,
oscillator is used the clock should be connected to the XI input and the XO pin left floating. When a
external clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using an
external clock the user needs to take care to ensure the external clock source is clean enough to not
degrade the high speed eye performance.
Once, the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz
clock.
The USB3290 includes an integrated set of built in power management functions. These power
management features include a POR generation and allow the USB3290 to be powered from a single
3.3 volt power supply. This reduces the bill of materials and simplifies product design.
Internal Regulators
The USB3290 has two integrated 3.3 volt to 1.8 volt regulators. These regulators require an external
4.7uF +/-20% low ESR bypass capacitor to ensure stability. X5R or X7R ceramic capacitors are
recommended since they exhibit an ESR lower than 0.1 ohm at frequencies greater than 10kHz.
The two regulator outputs, which require bypass capacitors, are the pins labeled VDDA1.8 and
VDD1.8. Each pin requires a 4.7uF bypass capacitor placed as close to the pin as possible.
Note: The USB3290 regulators are designed to generate a 1.8 volt supply for the USB3290 only.
Power On Reset (POR)
The USB3290 provides an internal POR circuit that generates a reset pulse once the PHY supplies
are stable.
Reset Pin
The UTMI+ Digital can be reset at any time with the RESET pin. The RESET pin of the USB3290 may
be asynchronously asserted and de-asserted so long as it is held in the asserted state continuously
for a duration greater than one CLKOUT cycle. The RESET input may be asserted when the USB3290
CLKOUT signal is not active (i.e. in the suspend state caused by asserting the SUSPENDN input) but
reset must only be de-asserted when the USB3290 CLKOUT signal is active and the RESET has been
held asserted for a duration greater than one CKOUT clock cycle. No other PHY digital input signals
may change state for two CLKOUT clock cycles after the de-assertion of the reset signal.
Using the regulators to provide current for other circuits is not recommended and SMSC does
not guarantee USB performance or regulator stability.
DATASHEET
27
Figure
Revision 1.5 (11-02-07)
8.10. If a clock