XR16L580IL-F Exar Corporation, XR16L580IL-F Datasheet
XR16L580IL-F
Specifications of XR16L580IL-F
Available stocks
Related parts for XR16L580IL-F
XR16L580IL-F Summary of contents
Page 1
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE MAY 2007 GENERAL DESCRIPTION The XR16L580 (L580 2.25 to 5.5 volt Universal Asynchronous Receiver and Transmitter (UART) with 5 volt tolerant inputs and a reduced pin count. It ...
Page 2
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE IGURE ACKAGES AND VCC 24-pin QFN Intel Bus mode D2 ...
Page 3
... REV. 1.4 IGURE ACKAGES AND CTS# 38 DSR# 39 CD# 40 RI# 41 VCC 42 48-TQFP Intel Bus Mode VCC ORDERING INFORMATION P N ART UMBER XR16L580IL24 XR16L580IL28 XR16L580IL XR16L580IM 48-Lead TQFP (48-TQFP P ) ACKAGE CTS DSR CD RI VCC 19 IOR GND 43 Motorola Bus Mode IOW XTAL2 XTAL1 D4 47 ...
Page 4
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE PIN DESCRIPTIONS Pin Descriptions 24- 28- 32- QFN QFN N QFN AME DATA BUS INTERFACE ...
Page 5
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 Pin Descriptions 24- 28- 32- QFN QFN N QFN AME RTS CTS# ...
Page 6
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE Pin Descriptions 24- 28- 32- QFN QFN N QFN AME RESET (RESET#) VCC GND ...
Page 7
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 1.0 PRODUCT DESCRIPTION The XR16L580 (L580 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its features set is compatible to the ST16C580 device and additionally offers ...
Page 8
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. ...
Page 9
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.2 5-Volt Tolerant Inputs The L580 can accept inputs when operating at 3.3V or 2.5V. But note that if the L580 is operating at 2.5V, ...
Page 10
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE T ABLE FCR (FIFO D ISABLED INT Pin data (16/68 byte IRQ# Pin ...
Page 11
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 F For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at http://www.exar.com. 2.9 Programmable Baud Rate Generator The L580 ...
Page 12
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE ABLE YPICAL DATA RATES WITH A O Data Rate O Data Rate UTPUT UTPUT MCR Bit-7=1 MCR Bit-7 DEFAULT 100 400 600 2400 1200 ...
Page 13
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.10 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts ...
Page 14
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE IGURE RANSMITTER PERATION IN Transmit Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1,2 and Xon1,2 Reg.) Auto Software Flow Control 16X ...
Page 15
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4 IGURE ECEIVER PERATION IN NON 16X Clock Receive Data Byte and Errors F 11 IGURE ECEIVER PERATION IN 16X Clock Receive Data ...
Page 16
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.12 Auto RTS (Hardware) Flow Control This feature is not available in the 24-QFN package since it does not have the RTS# pin. Automatic RTS hardware flow control is ...
Page 17
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 F 12. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to ...
Page 18
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled ( characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed ...
Page 19
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.17 Infrared Mode The L580 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the ...
Page 20
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 2.18 Sleep Mode with Wake-Up Interrupt and Power-Save Feature The L580 supports low voltage system designs, hence, a sleep mode with wake-up interrupt and Power-Save feature is included to ...
Page 21
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 2.19 Internal Loopback The L580 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic ...
Page 22
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 3.0 UART INTERNAL REGISTERS The L580 has a set of configuration registers selected by address lines A0, A1 and A2 with CS# asserted. The complete register set is shown ...
Page 23
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit-7 ...
Page 24
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE T 6: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto CTS Enable ...
Page 25
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR bit-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L580 in the FIFO ...
Page 26
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) This bit has no functionality in the 24-QFN package. • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 ...
Page 27
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4 ABLE P ISR R RIORITY EGISTER EVEL ...
Page 28
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic transmit FIFO reset (default). • Logic 1 = Reset ...
Page 29
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT ...
Page 30
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). This ...
Page 31
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 MCR[4]: Internal Loopback Enable • Logic 0 = Disable loopback mode (default). • Logic 1 = Enable local loopback mode, see loopback section and MCR[5]: Xon-Any Enable • ...
Page 32
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE LSR[4]: Receive Break Flag • Logic break condition (default). • Logic 1 = The receiver received a break signal (RX was a logic 0 for at ...
Page 33
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 MSR[4]: CTS Input Status CTS# pin may function as automatic hardware flow control signal input enabled and selected by Auto CTS (EFR bit-7). Auto CTS ...
Page 34
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE T ABLE EFR -3 EFR -2 EFR BIT BIT ONT ONT ...
Page 35
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 EFR[6]: Auto RTS Flow Control Enable This bit has no functionality in the 24-QFN package. RTS# output may be used for hardware flow control by setting EFR bit-6 ...
Page 36
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE T 11: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM and DLL Bits 15-0 = 0x0001. Resets upon power up only and not when only the ...
Page 37
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) Thermal Resistance (32-QFN) DC ...
Page 38
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE DC ELECTRICAL CHARACTERISTICS U : TA=-40 NLESS OTHERWISE NOTED S P YMBOL ARAMETER V Clock Input Low Level ILCK V Clock Input High Level IHCK V Input Low Voltage ...
Page 39
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 AC ELECTRICAL CHARACTERISTICS U : TA=-40 NLESS OTHERWISE NOTED S YMBOL - Crystal Frequency OSC External Clock Frequency CLK External Clock Low/High Time T Address Setup Time (16 ...
Page 40
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE AC ELECTRICAL CHARACTERISTICS U : TA=-40 NLESS OTHERWISE NOTED S YMBOL - Crystal Frequency OSC External Clock Frequency (with 2K pull-up on XTAL2) OSC External Clock Frequency (with XTAL2 ...
Page 41
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4 IGURE LOCK IMING CLK EXTERNAL CLOCK F 16 IGURE ODEM NPUT UTPUT IOW# RTS# Change of state DTR# CD# CTS# ...
Page 42
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE F 17 IGURE ODE NTEL ATA A0- A2 Address T AS CS# IOR# T RDV D0- IGURE ...
Page 43
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4 IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# T RWS R/W# T RDA D0- ...
Page 44
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE F 21 IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT IOR# (Reading data out of RHR IGURE RANSMIT EADY NTERRUPT ...
Page 45
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4 IGURE ECEIVE EADY NTERRUPT Start Bit RX S D0:D7 S D0:D7 Stop Bit INT T SSR IOR# (Reading data out of RX FIFO) ...
Page 46
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
Page 47
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL ...
Page 48
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE PACKAGE DIMENSIONS (28 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL ...
Page 49
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 PACKAGE DIMENSIONS (24 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL ...
Page 50
... May 2007 Rev 1.4.1 Updated QFN package dimensions drawing to show minimum "k" parameter. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
Page 51
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE REV. 1.4.1 GENERAL DESCRIPTION................................................................................................. 1 A ............................................................................................................................................... 1 PPLICATIONS F ..................................................................................................................................................... 1 EATURES ............................................................................................................................................................. 1 IGURE LOCK IAGRAM (24, 28 ...
Page 52
XR16L580 SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 4.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 25 4.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26 4.5.1 INTERRUPT GENERATION: ...................................................................................................................................... 26 4.5.2 INTERRUPT CLEARING: ........................................................................................................................................... 26 ...