XR16L580IL-F Exar Corporation, XR16L580IL-F Datasheet - Page 23

• Manufacturer Part Number: XR16L580IL-F
• Description: UART Interface IC UART
• Manufacturer: Exar Corporation

Specifications of XR16L580IL-F

• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• No. Of Channels: 1
• Uart Features: Selectable RX And TX FIFO Trigger Levels, Automatic Software Flow Control, Complete Modem Interface
• Supply Voltage Range: 2.25V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.4.1
.
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 0 0
0 0 1
T
ABLE
DREV
N
DVID
MCR
RHR
MSR
DLM
THR
FCR
LCR
SPR
R
LSR
DLL
IER
ISR
AME
EG
6: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
W
R
WR
WR
RD
RD
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
CTS Int.
Enabled
Enable
Trigger
Enable
Global
FIFOs
B
Pres-
BRG
caler
Error
Input
Bit-7
Bit-7
CD#
Bit-7
Bit-7
Bit-7
Bit-7
IT
0/
0/
0
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
-7
RX FIFO
IR Mode
RTS Int.
Enabled
ENable
Enable
Trigger
Set TX
THR &
FIFOs
Empty
Break
B
Input
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
TSR
RI#
IT
0/
0/
0
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
TX FIFO
Set Par-
XonAny
Xoff Int.
Enable
Source
Trigger
Empty
DSR#
B
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
Bit-5
INT
IT
ity
0/
0/
0/
0/
0
-5
23
TX FIFO
Internal
Source
Enable
Trigger
Enable
Break
Sleep
Mode
Parity
Loop-
CTS#
B
Even
Input
Bit-4
Bit-4
Bit-4
back
Bit-4
Bit-4
Bit-4
Bit-4
INT
RX
IT
0/
0/
0/
0
-4
S
HADED BITS ARE ENABLED WHEN
RX Fram-
INT Out-
ing Error
Stat. Int.
Modem
Source
(OP2#)
Enable
Enable
Enable
Enable
Mode
Parity
B
DMA
Delta
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
INT
put
IT
0
-3
RX Line
Enable
Source
(OP1#)
Reset
IR RX
Parity
Invert
B
FIFO
Delta
Error
Bit-2
Bit-2
Stat.
Bit-2
Stop
Bit-2
Bit-2
Bit-2
Bit-2
INT
Bits
RI#
Int.
RX
TX
IT
0
-2
Source
Control
Enable
Length
Output
Empty
Reset
DSR#
RTS#
Over-
B
Word
Delta
FIFO
Error
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
RX
RX
run
TX
Int
IT
0
-1
EFR B
Source
Control
Enable
Enable
Length
Output
Ready
FIFOs
DTR#
CTS#
B
Word
Delta
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
IT
1
-0
XR16L580
IT
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
DLM=0x00
DLL=0x00
C
LCR[7]=0
LCR[7]=1
LCR[7]=1
OMMENT