APA300-FGG256 Actel, APA300-FGG256 Datasheet - Page 113

• Manufacturer Part Number: APA300-FGG256
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-FGG256

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 290
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Number
M22
M14
M15
M16
M23
M24
M25
M26
Pin
P11
N11
N12
N13
N14
N15
N16
N22
N23
N24
N25
N26
P12
P13
P14
P15
N1
N2
N3
N4
N5
P1
P2
P3
P4
P5
PPECL1 / Input
I/O / GLMX1
I/O / GLMX2
Function
APA150
I/O / GL4
I/O / GL3
NPECL2
NPECL1
AGND
AGND
AVDD
AVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PPECL1 / Input
I/O / GLMX1
I/O / GLMX2
Function
APA300
I/O / GL4
I/O / GL3
NPECL2
NPECL1
AGND
AGND
AVDD
AVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
456-Pin PBGA
PPECL1 / Input
I/O / GLMX1
I/O / GLMX2
Function
APA450
I/O / GL4
I/O / GL3
NPECL2
NPECL1
AGND
AGND
AVDD
AVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
v5.9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PPECL1 / Input
I/O / GLMX1
I/O / GLMX2
Function
APA600
I/O / GL4
I/O / GL3
NPECL2
NPECL1
AGND
AGND
AVDD
AVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PPECL1 / Input
ProASIC
I/O / GLMX1
I/O / GLMX2
Function
APA750
I/O / GL4
I/O / GL3
NPECL2
NPECL1
AGND
AGND
AVDD
AVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PLUS
Flash Family FPGAs
PPECL1 / Input
I/O / GLMX1
I/O / GLMX2
APA1000
Function
I/O / GL4
I/O / GL3
NPECL2
NPECL1
AGND
AGND
AVDD
AVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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