APA300-FGG256 Actel, APA300-FGG256 Datasheet - Page 28

• Manufacturer Part Number: APA300-FGG256
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-FGG256

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 290
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLL Electrical Specifications
2 -1 8
Parameter
Frequency Ranges
Reference Frequency f
Reference Frequency f
OSC Frequency f
OSC Frequency f
Clock Conditioning Circuitry f
Clock Conditioning Circuitry f
Acquisition Time from Cold Start
Acquisition Time (max.)
Acquisition Time (max.)
Long Term Jitter Peak-to-Peak Max.*
Temperature
25°C (or higher)
0°C
–40°C
–55°C
Power Consumption
Analog Supply Power (max.*)
Digital Supply Current (max.)
Duty Cycle
Input Jitter Tolerance
Note: *High clock frequencies (>60 MHz) under typical setup conditions
ProASIC
PLUS
Flash Family FPGAs
VCO
VCO
(min.)
(max.)
IN
IN
(min.)
(max.)
OUT
OUT
(min.)
(max.)
2.0 MHz
180 MHz
60
180
f
f
180
80
80
Value T
IN
IN
≤ 40 = 18 MHz
> 40 = 16 MHz
μ
μ
s
s
J
≤
–40°C
v5.9
Value T
±1.5% ±2.5% ±1%
±2.5% ±3.5% ±1%
±2.5% ±3.5% ±1%
5% input period (max.
f
±1%
VCO
Frequency MHz
10
6.9 mW per PLL
50% ±0.5%
<
7
180 MHz
180 MHz
180 MHz
1.5 MHz
24 MHz
μ
6 MHz
30
80
J
CO
10<f
5 ns)
W/MHz
±2%
> –40°C
<60
μ
μ
s
s
V
f
±1% Jitter(ps) = Jitter(%)*period
>60
VCO
Clock conditioning circuitry (min.) lowest input
frequency
Clock conditioning circuitry (max.) highest input
frequency
Lowest output frequency voltage controlled
oscillator
Highest output frequency voltage controlled
oscillator
Lowest output frequency clock conditioning
circuitry
Highest output frequency clock conditioning
circuitry
f
f
For example:
Jitter in picoseconds at 100 MHz
= 0.01 * (1/100E6) = 100 ps
Maximum jitter allowable on an input
clock to acquire and maintain lock.
VCO
VCO
≤ 40 MHz
> 40 MHz
Notes