APA300-FGG256 Actel, APA300-FGG256 Datasheet - Page 171

• Manufacturer Part Number: APA300-FGG256
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-FGG256

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 290
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Previous version
v4.1
(continued)
v4.0
v3.5
v3.4
v3.3
Figure 2-27 • JTAG Operation Timing
Note 1 in
updated.
The notes in
were updated.
A note was added to
A note was added to
Industrial.
The
The
pin data.
Figure 2-17 • Using the PLL for Clock Deskewing
Table 2-48 • Recommended Operating Conditions
The
Pin names were changed to more accurately reflect the multiple functions supported by each
pin.
The ProASIC
document now supports Commercial, Industrial, and Military Temperature devices.
Table 1 • ProASICPLUS Product Profile
The
"Plastic Device Resources" table
The Long Term Jitter Peak-to-Peak Max. in the
The
"Performance Retention" section
Table 2-19 • Military Temperature Grade Product Performance Retention
Table 2-21 • Recommended Operating Conditions
Table 2-22 • DC Electrical Specifications (V
Table 2-24 • DC Electrical Specifications (V
to Military Temperature and MIL-STD-883B Temperature Only
Table 2-48 • Recommended Operating Conditions
The
The
The
The
The
The
The
Table 2-16 • Package Thermal Characteristics
The
The
The
Pin 15 = GLMX1
Pin 16 = GL1
Pin 21 = GL2
Pin 88 = GL3
Pin93 = GL4
Pin 94 = GLMX2
Changes in current version (v5.9)
"624-Pin CCGA/LGA" section
"TRST Test Reset Input" section
"1152-Pin FBGA" figure
"Ordering Information" section
"Calculating Typical Power Dissipation" section
"Temperature Grade Offerings" table
"Speed Grade and Temperature Matrix" table
"ProASIC
"Lock Signal" section
"PLL Electrical Specifications" table
"User Security" section
"Design Environment" section
"Asynchronous FIFO Full and Empty Transitions" section
"AVDD PLL Power Supply" section
"144-Pin TQFP" table
Table 2-52 • T
Table 2-56 • T
PLUS
PLUS
Clock Management System" section
and ProASIC
Figure 2-45 • FIFO
Table 2-68 • T
J
= 0°C to 110°C; V
was updated.
was updated. The following pins changed:
was updated.
J
was updated.
= 0°C to 110°C; V
was updated.
PLUS
was updated for the APA600 and APA1000. Please review all
was updated.
was updated in the
was updated.
J
is new.
= 0°C to 110°C; V
Military/Aerospace datasheets were combined. This
was updated.
in the
was updated.
Reset.
is new.
DDP
DDP
v5.9
DD
"Pin Description" section
"PLL Electrical Specifications" table
was updated.
= 3.3 V ±0.3 V and V
= 2.5 V ±0.2V)
= 2.3 V to 2.7 V for Commercial/Industrial
DD
was updated.
is new.
was updated.
was updated.
was updated.
was updated.
= 2.3 V to 2.7 V for Commercial/Industrial
was updated.
"Pin Description"
DD
was updated.
= 2.3 V to 2.7 V for Commercial/
was updated.
was updated.
DD
= 2.5 V ±0.2 V) Applies
was updated.
section.
ProASIC
was updated.
PLUS
was
Flash Family FPGAs
Page
2-53
2-55
2-59
2-72
2-72
2-73
3-78
2-16
2-52
3-69
2-18
2-28
2-31
2-32
2-33
2-34
2-38
2-52
2-10
2-13
2-18
2-20
2-25
2-27
2-65
2-73
3-4
iv
iv
ii
ii
i
4-3