AFS600-FGG256 Actel, AFS600-FGG256 Datasheet - Page 122

• Manufacturer Part Number: AFS600-FGG256
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG256

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 119
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
2- 10 6
From
calculation will first compute the post-calibration time, second the distribution time, and finally the STC
setting.
Since Actel recommends post-calibration for temperature drift over time, post-calibration shall be
enabled and the post-calibration time, t
0.24 µs.
The distribution time, t
The STC value can now be computed through
rearranging
And so, STC will be rounded up to 3 to ensure the minimum conversion time is met. The sample time,
t
The total sample time, using
The optimal setting for the system running at 66 MHz with an ADC for 10-bit mode chosen is listed as
follows:
*Note that no power-down after every conversion is chosen in this case; however, if the application is
power-sensitive, the MODE[2] can be set to '0', as described above, and it will not affect any
performance.
Integrated Voltage Reference
The Fusion device has an integrated on-chip 2.56 V reference voltage for the ADC. The value of this
reference voltage was chosen to make the prescaling and postscaling factors for the prescaler blocks
change in a binary fashion. However, if desired, an external reference voltage of up to 3.3 V can be
connected between the VAREF and GNDREF pins. The VAREFSEL control pin is used to select the
reference voltage.
Table 2-44 • VAREF Bit Function
sample
TVC[7:0]
STC[7:0]
MODE[3:0]
Name
VAREF
t
sync_read
Table 2-47 on page
, with an STC of 3, is now equal to 0.36 µs.
EQ 12 on page 2-104
+ t
Bit
0
= 1
= 3
= b'0100
sample
Reference voltage selection
0 – Internal voltage reference selected. VAREF pin outputs 2.56 V.
1 – Input external voltage reference from VAREF and GNDREF
+ t
distrib
t
= 1.8 µs – 0.24 µs – 1.2 µs – 0.15 µs – 0.15 µs = 0.32 µs
distrib
distrib
t
sample
2-122, minimum conversion for 10-bit mode is 1.8 µs. To compute STC, the
= 0x01
= 0x03
= 0x4*
, is equal to 1.2 µs and can be computed using
EQ
STC
+ t
=
N t
post-cal
= t
20, can now be summated.
×
with a t
conv
=
ADCCLK
t
-------------------- 2
t
post-cal
t
ADCCLK
+
sample
– t
post-cal
tsync_write
sample
post-cal
R e visio n 1
=
=
, can be computed by
–
10
= 1.85 µs
2
of 0.35 µs, the STC can be computed.
– t
×
=
×
= 0.015 µs + 0.36 µs + 1.2 µs + 0.24 µs + 0.015 µs
distrib
t
EQ
ADCCLK
0.12
0.35 µs
------------------- 2
0.12 µs
19. The sample time is equal to 0.32 µs. By
– t
Function
=
sync_read
1.2 µs
=
–
0.24 µs
=
2.85
– t
EQ
sync_write
17. The post-calibration time is
EQ
18.
EQ 17
EQ 18
EQ 19
EQ 20