XC3S1400AN-4FGG484C Xilinx Inc, XC3S1400AN-4FGG484C Datasheet - Page 15

• Manufacturer Part Number: XC3S1400AN-4FGG484C
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484C

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General DC Characteristics for I/O Pins
Table 11: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
Symbol
I
I
R
R
RPU
RPD
I
I
R
C
I
PU
PD
REF
L
HS
DT
The numbers in this table are based on the conditions set forth in
For single-ended signals that are placed on a differential-capable I/O, V
between the two pins. See Parasitic Leakage in UG331, Spartan-3 Generation FPGA User Guide.
This parameter is based on characterization. The pull-up resistance R
V
(2)
IN
(3)
(3)
CCAUX
(3)
(3)
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Leakage current on pins during
hot socketing, FPGA unpowered
Current through pull-up resistor
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins.
Dedicated pins are powered by
V
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on I
Current through pull-down
resistor at User I/O,
Dual-Purpose, Input-only, and
Dedicated pins
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on I
V
Input capacitance
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
must be 3.3V on Spartan-3AN FPGAs. V
CCAUX
REF
current per pin
.
(4)
Description
RPU
RPD
per Note 3)
per Note 3)
Driver is in a high-impedance state,
V
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0.
V
IN
V
V
CCAUX
CCO
CCO
= 0V or V
CCAUX
V
V
V
= 3.3V
= 2.5V
IN
IN
IN
= 3.0V to 3.6V
= GND
= V
= GND
for Spartan-3A FPGAs can be either 3.3V or 2.5V.
CCO
www.xilinx.com
CCO
±
±
Spartan-3AN FPGA Family: DC and Switching Characteristics
Test Conditions
max, sample-tested
10%
10%
All V
Table
CCO
PU
IN
–
10.
= V
of –0.2V to –0.5V is supported but can cause increased leakage
V
V
levels
V
V
V
V
V
V
V
V
V
CCO
CCO
CCAUX
V
V
V
V
V
IN
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
MINI_LVDS_33,
MINI_LVDS_25,
CCO
IN
IN
IN
IN
= 1.14V to 1.26V
3.0V to 3.6V
= 1.14V to 1.26V
= 1.14V to 1.26V
= 3.0V to 3.6V
= 2.3V to 2.7V
= 1.7V to 1.9V
= 1.4V to 1.6V
LVDS_33,
RSDS_33
LVDS_25,
RSDS_25
/ I
= 2.3V to 2.7V
= 1.7V to 1.9V
= 1.4V to 1.6V
= 3.0V to 3.6V
= 2.3V to 2.7V
= 1.7V to 1.9V
= 1.4V to 1.6V
or V
= 3.0V to 3.6V
RPU
. The pull-down resistance R
CCAUX
=
–151
10.8
15.3
Min
–10
–10
–82
–36
–22
–11
167
–10
5.1
6.2
8.4
5.5
4.1
3.0
2.7
2.4
90
90
–
Add I
–315
–182
11.4
14.8
21.6
28.4
41.1
10.4
HS
Typ
–88
–56
–31
346
100
110
7.8
5.7
5.1
4.5
–
–
–
–
PD
+ I
= V
RPU
IN
119.4
–710
–437
–226
–148
Max
23.9
33.1
52.6
20.8
15.7
11.1
74.0
+10
+10
–83
659
+10
115
9.6
8.1
10
/ I
–
RPD
.
Units
k
k
k
k
k
k
k
k
k
k
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
pF


15