MR25H10CDC EverSpin Technologies Inc, MR25H10CDC Datasheet

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... The MR25H10 is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as 131,072 words of 8 bits. The MR25H10 offers serial EEPROM and serial Flash compatible read/write timing with no write delays and unlimited read/write endurance. Unlike other serial memories, both reads and writes can occur randomly in memory with no delay between writes. The MR25H10 is the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of I/O pins The MR25H10 is available in a small footprint 8-pin DFN package that is compatible with serial EEPROM, Flash, and FeRAM products. The MR25H10 provides highly reliable data storage over a wide range of temperatures. The product is offered with industrial temperature (-40° to +85 °C), and automotive temperature (-40° to +125° C) range options ...

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... DEVICE PIN ASSIGNMENT Overview The MR25H10 is a serial MRAM with memory array logically organized as 128Kx8 using the four pin in- terface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral interface (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and Flash components allowing MRAM to replace these components in the same socket and interoperate on a shared SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating power, and more reliable data retention compared to available serial memory alternatives HOLD SCK SI System Configuration Single or multiple devices can be connected to the bus as show in Figure 1.2. Pins SCK, SO and SI are com- mon among devices. Each device requires CS and HOLD pins to be driven seperately. Everspin Technologies © ...

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... A low on the Hold pin interrupts a memory operation for another task. When HOLD is low, the current operation is suspended. The device will ignore transitions on the CS and SCK when HOLD is low. All transitions of HOLD must occur while CS is low. Power supply voltage from +2.7 to +3.6 volts. ...

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... Exit Sleep Mode Status Register The status register consists of the 8 bits listed in table 2.1. As seen in table 2.2, the Status Register Write Disable bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) to provide hardware memory block protection. Bits BP0 and BP1 define the memory block arrays that are protected as described in table 2.3. The fast writing speed of MR25H10 does not require write status bits. The state of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the status register are pre-set from the factory in the “0” state. Bit 7 Bit 6 Bit 5 SRWD Don’t Care Don’ ...

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... SCK High Impedance Everspin Technologies © 2009 Table 2.3 Memory Protection Modes Protected Blocks Unprotected Blocks Protected Protected Protected Writable Protected Writable Protected Writable Table 2.4 Block Memory Write Protection Protected Area None Upper Quarter Upper Half All Figure 2.1 RDSR MSB 7 MSB ...

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... CS Mode 3 SCK Mode Write Disable (WRDI) The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 7). This prevents writes to status register or memory. The WRDI command is entered by driving CS low, send- ing the command code, and then driving CS high. The Write Enable Latch (WEL) is reset on power-up or when the WRDI command is completed. CS Mode 3 SCK Mode Write Status Register (WRSR) The Write Status Register (WRSR) command allows new values to be written to the Status Register ...

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... SO Read Data Bytes (READ) The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the 24-bit address. Only address bits 0-16 are decoded by the memory. The data bytes are read out sequen- tially from memory until the read operation is terminated by bringing CS high The entire memory can be read in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. The READ command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi- nated by bring CS high SCK ...

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... SPI COMMUNICATIONS PROTOCOL Write Data Bytes (WRITE) The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by the 24-bit address. Only address bits 0-16 are decoded by the memory. The data bytes are written sequen- tially in memory until the write operation is terminated by bringing CS high. The entire memory can be written in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed without write delays or data polling. Back to back WRITE commands to any random location in mem- ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or block organized memory ideal for both program and data storage ...

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... The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall chip standby power to 3 μA typical. The SLEEP command is entered by driving CS low, sending the com- mand code, and then driving CS high. The standby current is achieved after time SCK Exit Sleep Mode (WAKE) The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation. The WAKE command is entered by driving CS low, sending the command code, and then driving CS high. The memory returns to standby mode after SCK Everspin Technologies © 2009 Figure 2.7 SLEEP ...

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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the field intensity specified in the maximum ratings. Parameter Supply voltage 2 Voltage on any pin 2 Output current per pin Package power dissipation Temperature under bias MR25H10C (Industrial) MR25H10M (Automotive) Storage Temperature Lead temperature during solder (3 minute max) Maximum magnetic field during write Maximum magnetic field during read or standby Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera- 1 tion should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. All voltages are referenced than 0.5V. The AC value less than 20mA. Power dissipation capability depends on package characteristics and use environment. 3 Automotive temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 4 20-year life). Everspin Technologies ...

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ELECTRICAL SPECIFICATIONS Parameter Power supply voltage Input high voltage Input low voltage Temperature under bias MR25H10C (Industrial) MR25H10M (Automotive) Parameter Input leakage current Output leakage current Output low voltage ( mA +100 μA) OL Output high voltage ( mA -100 μA) OH Parameter Active Read Current (@ 1 MHz) Active Read Current (@ 40 MHz) Active Write Current (@ 1 MHz) Active Write Current (@ 40 MHz) Standby Current (CS High) Standby Sleep Mode Current (CS High) Automotive I TBD. 1 SB2 Everspin Technologies © 2009 Table ...

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TIMING SPECIFICATIONS Parameter Control input capacitance Input/Output capacitance ƒ = 1.0 MHz 3 °C, periodically sampled rather than 100% tested Parameter Logic input timing measurement reference level Logic output timing measurement reference level Logic input pulse levels Input rise/fall time Output load for low and high impedance parameters Output load for all other timing parameters Figure 4.1 Output Load for Impedance Parameter Measurements Output Figure 4.2 Output Load for all Other Parameter Measurements Everspin Technologies © 2009 Table 4.1 Capacitance ...

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TIMING SPECIFICATIONS Power-Up Timing The MR25H10 is not accessible for a start-up time, t from the time when V (min) is reached until the first CS low to allow internal voltage references to become DD stable. The CS signal should be pulled sequence. Parameter Write Inhibit Voltage Startup Time (max (min) DD Reset state of the device V WI Everspin Technologies © 2009 = 400 μs after power up. Users must wait this time PU so that the signal tracks the power supply during power-up DD Table 4.3 Power-Up Symbol Min ...

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TIMING SPECIFICATIONS Synchronous Data Timing Parameter SCK Clock Frequency Input Rise Time Input Fall Time SCK High Time SCK Low Time Synchronous Data Timing (See figure 4.4) CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Output Valid 2 Output Hold Time HOLD Timing (See figure 4.5) HOLD Setup Time HOLD Hold Time HOLD to Output Low Impedance HOLD to Output High Impedance Other Timing Specifications WP Setup Hold From CS Sleep Mode Entry Time Sleep Mode Exit Time Output Disable Time Operating Temperature Range Automotive t is TBD. 2 ...

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TIMING SPECIFICATIONS CSS V IH SCK High Impedance SCK HOLD SO Everspin Technologies © 2009 Figure 4.4 Synchronous Data Timing ...

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... ORDERING INFORMATION MR 25H Part Number MR25H10CDC MR25H10MDC MR25H10CDCR MR25H10MDCR Preliminary - This is a product in development that has fixed target specifications that are subject to change pending characterization results. Everspin Technologies © 2009 Figure 4.1 Part Numbering System Package Options DC 8 Pin DFN on Tray DCR 8 Pin DFN on Tape and Reel Temperature Range C Industrial (-40 to +85 °C ambient) M Automotive (-40 to +125 °C ambient) Memory Density Interface ...

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MECHANICAL DRAWINGS A B Pin 1 Index C D Unit Max 5.10 6.10 1.00 - Min 4.90 5.9 0.90 NOTE: 1. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229 Everspin Technologies © 2009 Figure 6.1 DFN Package Detail A F ...

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REVISION HISTORY Revision Date 0 Sep 12, 2008 1 Jul 10, 2009 2 Jul 16, 2009 3 Jan 5, 2010 4 Feb 5, 2010 5 May 17, 2010 Preliminary - This is a product in development that has fixed target specifications that are subject to change pending characterization results. How to Reach Us: Home Page: www.everspin.com E-Mail: support@everspin.com orders@everspin.com sales@everspin.com USA/Canada/South and Central America Everspin Technologies 1300 N. Alma School Road, CH-409 Chandler, Arizona 85224 +1-877-347-MRAM (6726) +1-480-347-1111 Europe, ...