SST25LF020A-33-4C-SAE Microchip Technology, SST25LF020A-33-4C-SAE Datasheet - Page 14

• Manufacturer Part Number: SST25LF020A-33-4C-SAE
• Description: IC FLASH SER 2MB 33HZ SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of SST25LF020A-33-4C-SAE

• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Format - Memory: FLASH
• Speed: 33MHz
• Interface: SPI Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Architecture: Sectored
• Interface Type: SPI
• Access Time: 33 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 10 mA
• Mounting Style: SMD/SMT
• Organization: 4 KB x 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Data Sheet
Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows read-
ing of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
©2010 Silicon Storage Technology, Inc.
FIGURE 11: Chip-Erase Sequence
FIGURE 12: Read-Status-Register (RDSR) Sequence
SCK
CE#
SO
SI
MODE 3
MODE 0
MSB
0
1
HIGH IMPEDANCE
2
SCK
CE#
3
SO
05
SI
MODE 3
MODE 0
4
5
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
6
14
7
by executing an 8-bit command, 60H. CE# must be driven
high before the instruction is executed. The user may poll
the Busy bit in the software status register or wait T
the completion of the internal self-timed Chip-Erase cycle.
See Figure 11 for the Chip-Erase sequence.
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-
Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 12 for the RDSR instruction sequence.
60
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
8
9
1242 F10.0
10
Register Out
11
Status
12
2 Mbit SPI Serial Flash
13
14
1242 F11.0
SST25LF020A
S71242-07-000
CE
01/10
for