SST25LF020A-33-4C-SAE Microchip Technology, SST25LF020A-33-4C-SAE Datasheet - Page 4
SST25LF020A-33-4C-SAE
Manufacturer Part Number
SST25LF020A-33-4C-SAE
Description
IC FLASH SER 2MB 33HZ SPI 8SOIC
Manufacturer
Microchip Technology
Datasheet
1.SST25LF020A-33-4C-SAE.pdf
(25 pages)
Specifications of SST25LF020A-33-4C-SAE
Memory Type
FLASH
Memory Size
2M (256K x 8)
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Format - Memory
FLASH
Speed
33MHz
Interface
SPI Serial
Voltage - Supply
3 V ~ 3.6 V
Architecture
Sectored
Interface Type
SPI
Access Time
33 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
10 mA
Mounting Style
SMD/SMT
Organization
4 KB x 64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SST25LF020A-33-4C-SAE
Manufacturer:
MICROCHIPS
Quantity:
10 002
Part Number:
SST25LF020A-33-4C-SAE
Manufacturer:
SST
Quantity:
20 000
Company:
Part Number:
SST25LF020A-33-4C-SAE-T
Manufacturer:
HITACHI
Quantity:
651
Part Number:
SST25LF020A-33-4C-SAE-T
Manufacturer:
SST
Quantity:
20 000
Data Sheet
PRODUCT IDENTIFICATION
TABLE 2: Product Identification
MEMORY ORGANIZATION
The SST25LF020A SuperFlash memory array is orga-
nized in 4 KByte sectors with 32 KByte overlay blocks.
©2010 Silicon Storage Technology, Inc.
Manufacturer’s ID
Device ID
FIGURE 3: SPI Protocol
SST25LF020A
SCK
CE#
SO
SI
MODE 3
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1Bit 0
MSB
HIGH IMPEDANCE
Address
00000H
00001H
Data
BFH
43H
T2.0 1242
4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
DEVICE OPERATION
The SST25LF020A is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
The SST25LF020A supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 3, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
DON'T CARE
2 Mbit SPI Serial Flash
MODE 3
MODE 0
SST25LF020A
S71242-07-000
1242 F02.0
01/10