LMH1982SQEEVAL/NOPB National Semiconductor, LMH1982SQEEVAL/NOPB Datasheet - Page 4

• Manufacturer Part Number: LMH1982SQEEVAL/NOPB
• Description: EVAL BOARD FOR LMH1982SQE
• Manufacturer: National Semiconductor

Specifications of LMH1982SQEEVAL/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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1.6.1 VCXO Power Supply Considerations
The VCXO and LMP7701 devices operate from a separate
supply plane (VDD_VCXO) derived from the board’s 3.3V
supply. Resistor R5 is used to form a low-pass filter with the
associated decoupling and bypass capacitors to attenuate
supply noise to these devices. Refer to the VCXO power sup-
ply and ground routing in the PCB layout section.
1.7 FREE RUN CONTROL VOLTAGE INPUT
The LMH1982 provides the option to set the VCXO's free run
control voltage by external biasing of the VC_FREERUN input
(pin 1). The analog bias voltage applied to the VC_FREERUN
input will be internally connected to the LPF output (pin 31)
though a low impedance switch when the LMH1982 is oper-
ating in free run. The resultant voltage at the LPF output will
drive the VCXO control input to set the free run output fre-
quency accuracy of the VCXO and LMH1982. The
VC_FREERUN input should have low noise and sufficient fil-
tering to minimize VCXO input voltage modulation, which can
result in excessive VCXO and output clock jitter during free
run operation.
The 50K potentiometer P1 can be adjusted to set the input
voltage to VC_FREERUN between GND and VDD. A
LMP7701 (U8) op amp is used to buffer the voltage divider
from P1. As an alternative to using P1, an external voltage
can be applied to header JP5 to set the VC_FREERUN volt-
age; however, you must initially remove P1 and short R27.
1.8 CONTROL INPUTS
Switch SW1 allows the LMH1982 control inputs to be set to
logic high (VDD) or logic low (GND). See for the toggle switch
definitions for SW1.
FIGURE 2. PCB Layout showing Loop Filter and VCXO
SWITCH LABEL
GENLOCK
REF_SEL
I2C_ENA
RESET
TABLE 6. Control Input Switch, SW1
Reset operation
Genlock Mode
Select REF_A
Enable I
LOW
2
C
Normal operation
Free Run Mode
Select REF_B
Disable I
HIGH
30061910
2
C
4
Note: The REF_SEL and GENLOCK inputs will only be functional after they
have been enabled by programming the control registers.
During normal operation, the RESET input must be set high;
otherwise the device will not function properly. To reset the
control registers of the LMH1982, toggle RESET low for at
least 10 µs for proper reset and then set high.
To enable programming via the I
ABLE input must be set low. If I2C_ENABLE is set high and
any attempt is made to communicate via I
will not acknowledge, and read/write operations will not occur.
The control inputs can be probed on the inside pins of header
J9, while the edge-side pins of J9 are all connected to GND.
See Table 7 for the pin assignments of J9. If SW1 is removed,
J9 may also be used to apply external logic signals to the
control inputs.
1.9 GENLOCK STATUS INDICATION
The evaluation board has two green LEDs (D3, D4) for visual
indication of the PLL lock status and reference status outputs,
NO_LOCK and NO_REF. In Genlock mode, the PLL lock sta-
tus is indicated by D3 (labeled “GENLOCKED”) and the ref-
erence status is indicated by D4 (labeled “REFERENCE”).
The NO_LOCK and NO_REF outputs can be probed respec-
tively at pins 7 and 8 of header J10.
Refer to the LMH1982 datasheet for more information about
programming the PLL lock threshold and loss of reference
threshold.
Genlock mode
Reference lost
PLL(s) not locked
Genlock mode
Reference valid
PLL(s) locking
Genlock mode
Reference valid
PLLs locked
Pin #
1
2
3
4
Condition
TABLE 7. Control Input Test Points, J9
TABLE 8. Genlock Status LEDs
Pin Name
GND
GND
GND
GND
(NO_LOCK)
OFF
OFF
2
ON
D3
C interface, the I2C_EN-
Pin #
8
7
6
5
2
C, the LMH1982
I2C_ENABLE
(NO_REF)
GENLOCK
Pin Name
REF_SEL
RESET
OFF
ON
ON
D4