FT245RL-REEL FTDI, FT245RL-REEL Datasheet - Page 12

• Manufacturer Part Number: FT245RL-REEL
• Description: USB Interface IC USB to Parallel FIFO Enhanced IC SSOP-28
• Manufacturer: FTDI
• Type: USB to Parallel FIFOr

Specifications of FT245RL-REEL

• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Operating Supply Voltage: 1.8 V to 5.25 V
• Description/function: USB to Parallel FIFO Enhanced IC SSOP-28
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 25 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin
No.
6
7
8
9
11
21
22
Table 3.8 FIFO Interface Group (see note 3)
Notes:
10
1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when
2.
3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ
using the internal clock generator. Operation at +3.3V is possible using an external
crystal oscillator.
For details on how to use an external crystal, ceramic resonator, or oscillator with the
please refer to
resistors. These pins can be programmed to gently pull low during USB suspend (
PWREN# = “1”) by setting an option in the internal EEPROM.
Name
D5
D6
D3
PWREN#
WR
TXE#
RXF#
RD#
Copyright © 2010 Future Technology Devices International Limited
Type
I/O
I/O
I/O
Output
Input
Output
Output
Input
Section 8.2
Description
FIFO Data Bus Bit 5
FIFO Data Bus Bit 6
FIFO Data Bus Bit 3
Goes low after the device is configured by USB, then high during USB
suspend. Can be used to control power to external logic P-Channel logic
level MOSFET switch. Enable the interface pull-down option when using the
PWREN# pin in this way. Should be pulled to VCCIO with 10kΩ resistors.
Enables the current FIFO data byte from D0…D7 when low. Fetched the next
FIFO data byte (if available) from the receive FIFO buffer when RD# goes
from high to low. See Section 3.5 for timing diagram.
Writes the data from byte from D0...D7 pins into the transmit FIFO buffer
when WR goes from high to low. See section 3.6 for timing diagram.
When high, do not write data into the FIFO. When low, data can be written
into the FIFO by strobing WR high, then low. During reset this signal pin is
tri-state. See Section 3.6 for timing diagram.
When high, do not read data from the FIFO. When low, there is data
available in the FIFO which can be read by strobing RD# low, then high
again. During reset this signal pin is tri-state. See Section 3.5 for timing
diagram.
If the Remote Wakeup option is enabled in the internal EEPROM, during USB
suspend mode (PWREN# = 1) RXF# becomes an input. This can be used to
wake up the USB host from suspend mode by strobing this pin low for a
minimum of 20ms which will cause the device to request a resume on the
USB bus.
FT245R USB FIFO IC Datasheet Version 2.10
Document No.: FT_000052
Clearance No.: FTDI# 39
FT245R,
12