EVAL-ADF7012DBZ3 Analog Devices Inc, EVAL-ADF7012DBZ3 Datasheet - Page 22

• Manufacturer Part Number: EVAL-ADF7012DBZ3
• Description: BOARD EVALUATION DB3 FOR ADF7012
• Manufacturer: Analog Devices Inc
• Type: Transmitterr

Specifications of EVAL-ADF7012DBZ3

• Frequency: 1GHz
• For Use With/related Products: ADF7012
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF7012
868 MHz OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to ETSI site testing.
Matching components need to be adjusted for board layout.
The ETSI standard EN 300-220 governs operation in the
868 MHz to 870MHz band. The band is broken down into
several subbands each having a different duty cycle and output
power requirement. Narrowband operation is possible in the
50kHz channels, but both the output power and data rate are
limited by the −36 dBm adjacent channel power specification.
There are many different applications in this band, including
remote controls for security, sensor interrogation, metering
and home control.
Design Criteria
868.95 MHz center frequency (band 868.7MHz − 869.2 MHz)
FSK modulation
12 dBm output power
300 m range
Meets ETSI 300-220
38.4 kbps data rate
The design challenge is to enable the part to operate in this
particular subband and meet the ACP requirement 250 kHz
away from the center.
The center frequency is 868.95 MHz. It is possible to operate the
VCO at this frequency. Figure 31 shows the inductor value vs.
center frequency. The inductor chosen is 1.9 nH. Coilcraft
inductors such as 0402-CS-1N9XJBU are recommended.
Crystal and PFD
The phase noise requirement is such to ensure the power at
the edge of the band is < −36 dBm. This requires close to
−100 dBc/Hz phase noise at the edge of the band.
The PFD is chosen to minimize spurious levels (beat note and
reference), and to ensure a quick crystal power-up time. A PFD
of < 6 MHz places the largest PFD spur at a frequency of greater
than 862 MHz, and so reduces the requirement on the spur
level to −36 dBm instead of −54 dBm.
PFD = 4.9152 MHz − Power Up-Time 1.6 ms. Figure 10 shows a
typical power-on time for a 4MHz crystal.
N-Divider
The N divider is determined as being:
Nint = 176
Nfrac = (3229)/4096
VCO divide-by-2 is not enabled.
Rev. A | Page 22 of 28
Deviation
The deviation is set to ±19.2 kHz to accommodate a simple
receiver architecture and ensure that the modulation spectrum
is narrow enough to meet the adjacent channel power (ACP)
requirements.
The modulation steps available are in 4.9152 MHz/2
Bias Current
Because low current is desired, a 2.5 mA VCO bias can be used.
Additional bias current reduces any spurious, but increases
current consumption. A 2.5 mA bias current gives the best
spurious vs. phase noise trade-off.
The PA bias should be set to 7.5 mA to achieve 12 dBm.
Loop Filter Bandwidth
The loop filter is designed with ADIsimSRD Design Studio.
The loop bandwidth design requires that the channel power be
< −36 dBm at ±250 kHz from the center. A loop bandwidth of
close to <60 kHz is required to bring the phase noise at the edge
of the band sufficiently low to meet the ACP specification. This
represents a compromise between the data rate requirement and
the phase noise requirement.
Design of Harmonic Filter
The main requirement of the harmonic filter should ensure that
the second and third harmonic levels are < −30 dBm. A fifth-
order Chebyshev filter is recommended to achieve this, and a
suggested starting point is given next. The Pi format is chosen
to minimize the more expensive inductors.
Component Values—Crystal: 4.9152 MHz
Loop Filter
Icp
LBW
C1
C2
C3
R1
R2
Matching
L1
L2
C14
Harmonic Filter
L4
L5
C15
C16
C17
Modulation steps = 300 Hz
Modulation number = 19.2 kHz/300 Hz = 64.
1.44 mA
60 kHz
1.5 nF
22 nF
560 pF
390 Ω
910 Ω
27 nH
6.2 nH
470 pF
8.2 nH
8.2 nH
4.7 pF
6.8 pF
4.7 pF
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