LFXP6C-5TN144C LATTICE SEMICONDUCTOR, LFXP6C-5TN144C Datasheet - Page 17

• Manufacturer Part Number: LFXP6C-5TN144C
• Description: FPGA, 1.8V FLASH, INSTANT ON, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: LatticeXPr

Specifications of LFXP6C-5TN144C

• No. Of Logic Blocks: 720
• No. Of Macrocells: 3000
• Family Type: LatticeXP
• No. Of Speed Grades: 5
• No. Of I/o's: 100
• Clock Management: PLL
• Core Supply Voltage Range: 1.71V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-15. Memory Core Reset
For further information on sysMEM EBR block, see the details of additional technical documentation at the end of
this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-16. The GSR input to the
EBR is always asynchronous.
Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
Programmable I/O Cells (PICs)
Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
buffer, and receives input from the buffer.
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-14
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
LatticeXP Family Data Sheet
Port A[17:0]
Port B[17:0]
MAX
(EBR clock). The reset
Architecture