IS43DR16320B-3DBL

Manufacturer Part NumberIS43DR16320B-3DBL
DescriptionSDRAM, DDR2, 32M X 16, 1.8V, 84BGA
ManufacturerINTEGRATED SILICON SOLUTION (ISSI)
IS43DR16320B-3DBL datasheet
 

Specifications of IS43DR16320B-3DBL

Access Time0.45nsPage Size512Mbit
Memory Case StyleBGANo. Of Pins84
Operating Temperature Range-40°C To +105°CMemory TypeSDRAM
Memory Configuration4 BLK (8M X 16)Frequency333MHz
Rohs CompliantYesLead Free Status / RoHS StatusLead free / RoHS Compliant
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IS43/46DR86400B, IS43/46DR16320B
512Mb (x8, x16) DDR2 SDRAM
FEATURES
Clock frequency up to 400MHz
Posted CAS
Programmable CAS Latency: 3, 4, 5 and 6
Programmable Additive Latency: 0, 1, 2, 3, 4 and 5
Write Latency = Read Latency-1
Programmable Burst Sequence: Sequential or
Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 µs (8192 cycles/64 ms)
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Weak Strength Data-Output Driver Option
Bidirectional differential Data Strobe (Single-
ended data-strobe is an optional feature)
OPTIONS
• Configuration:
64Mx8 (16M x 8 x 4 banks)
32Mx16 (8M x 16 x 4 banks)
• Package:
60-ball FBGA for x8
84-ball FBGA for x16
Clock Cycle Timing
-5B
Speed Grade
DDR2-400B
CL-tRCD-tRP
3-3-3
tCK (CL=3)
5
tCK (CL=4)
5
tCK (CL=5)
5
tCK (CL=6)
5
Frequency (max)
200
Note: The -5B device specification is shown for reference only.
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
On-Chip DLL aligns DQ and DQs transitions with
CK transitions
Differential clock inputs CK and CK#
VDD and VDDQ = 1.8V ± 0.1V
PASR (Partial Array Self Refresh)
SSTL_18 interface
tRAS lockout supported
Read Data Strobe supported (x8 only)
Internal four bank operations with single pulsed
RAS
Operating temperature:
Commercial (T
Industrial (T
Automotive, A1 (T
+95°C)
Automotive, A2 (T
to +105°C)
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Precharge Addressing
-37C
-3D
DDR2-533C
DDR2-667D
4-4-4
5-5-5
5
5
3.75
3.75
3.75
3
3.75
3
266
333
JANUARY 2011
= 0°C to +70°C ; T
= 0°C to +85°C)
A
C
= -40°C to +85°C; T
= -40°C to +95°C)
A
C
= -40°C to +85°C; T
= -40°C to
A
C
= -40°C to +105°C; T
= -40°C
A
C
64Mx8
32Mx16
A0-A13
A0-A12
A0-A9
A0-A9
BA0-BA1
BA0-BA1
A10
A10
-25E
-25D
DDR2-800E
DDR2-800D
6-6-6
5-5-5
5
5
3.75
3.75
3
2.5
2.5
2.5
400
400
Units
tCK
ns
ns
ns
ns
MHz
1

IS43DR16320B-3DBL Summary of contents

  • Page 1

    IS43/46DR86400B, IS43/46DR16320B 512Mb (x8, x16) DDR2 SDRAM FEATURES • Clock frequency up to 400MHz • Posted CAS • Programmable CAS Latency and 6 • Programmable Additive Latency and 5 • Write Latency ...

  • Page 2

    IS43/46DR86400B, IS43/46DR16320B Package Ball-out and Description DDR2 SDRAM (64Mx8) 60-ball BGA Ball-out (Top-View) (10. 10.50 mm Body, 0.8 mm pitch) Symbol Description CK, CK# Input clocks CKE Clock enable CS# Chip Select RAS#,CAS#,WE# Command control pins A[13:0] Address ...

  • Page 3

    IS43/46DR86400B, IS43/46DR16320B DDR2 SDRAM (32Mx16) 84-ball BGA Ball-out (Top-View) (10. 13.00 mm Body, 0.8 mm pitch) Symbol Description CK, CK# Input clocks CKE Clock enable CS# Chip Select RAS#,CAS#,WE# Command control inputs A[12:0] Address BA[1:0] Bank Address DQ[15:0] ...

  • Page 4

    IS43/46DR86400B, IS43/46DR16320B Functional Description Power-up and Initialization DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence The following sequence is required for ...

  • Page 5

    IS43/46DR86400B, IS43/46DR16320B Initialization Sequence after Power-Up Diagram tCH tCL ~ ~ CK tIS CK ODT ~ ~ PRE Command ~ NOP EMRS ALL 400ns tRP DLL Enable Programming the Mode Register and Extended Mode Registers For application ...

  • Page 6

    IS43/46DR86400B, IS43/46DR16320B Mode Register (MR) Diagram Address Mode Field Register BA1 0 BA0 0 (1) 0 A13 A12 PD1 A11 A10 DLL CAS A5 Latency Burst A1 Length A0 Notes: ...

  • Page 7

    IS43/46DR86400B, IS43/46DR16320B DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh ...

  • Page 8

    IS43/46DR86400B, IS43/46DR16320B be changed using the same command and clock cycle requirements during normal operation as long as all banks are in precharge state. Extended Mode Register 2 (EMR[2]) Diagram Address Mode Field Register BA1 1 BA0 0 (1) 0 ...

  • Page 9

    IS43/46DR86400B, IS43/46DR16320B DDR2 Extended Mode Register 3 (EMR[3]) Diagram Address Field BA1 Mode Register 1 Note: All bits in EMR[3] except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR[3]. Truth ...

  • Page 10

    IS43/46DR86400B, IS43/46DR16320B Clock Enable (CKE) Truth Table (2) Current State (1) Previous Cycle (N-1) L Power Down L L Self Refresh L Bank(s) Active H H All Banks Idle H H Notes: 1. CKE (N) is the logic state of ...

  • Page 11

    IS43/46DR86400B, IS43/46DR16320B Commands DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT. ...

  • Page 12

    IS43/46DR86400B, IS43/46DR16320B required. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a REFRESH command. SELF REFRESH The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, ...

  • Page 13

    IS43/46DR86400B, IS43/46DR16320B 3. ODT turn off time min, tAOF(Min), is when the device starts to turn off the ODT resistance. ODT turn off time max, tAOF(Max) is when the bus is in high impedance. Both are measured from tAOFD. Integrated ...

  • Page 14

    IS43/46DR86400B, IS43/46DR16320B ODT Timing for Precharge Power-Down Mode 0 CK# CK CKE ODT Internal Term. Resistance Note: Both ODT to Power Down Endtry and Exit Latencies tANPD and tAXPD are not met, therefore Power-Down Mode timings have to be applied. ...

  • Page 15

    IS43/46DR86400B, IS43/46DR16320B Absolute Maximum DC Ratings Symbol VDD Voltage on VDD pin relative to Vss VDDQ Voltage on VDDQ pin relative to Vss VDDL Voltage on VDDL pin relative to Vss Vin, Vout Voltage on any pin relative to Vss ...

  • Page 16

    IS43/46DR86400B, IS43/46DR16320B AC and DC Logic Input Levels Single-ended DC Input Logic Level Symbol VIH(DC) VIL(DC) Single-ended AC Input logic level Symbol Parameter VIH(AC) AC input logic HIGH VIL(AC) AC input logic LOW Note: Refer to Overshoot and Undershoot Specification ...

  • Page 17

    IS43/46DR86400B, IS43/46DR16320B Differential Signal Level Waveform Differential AC Output Parameters Symbol Parameter VOX(AC) AC differential crosspoint voltage Note: The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to ...

  • Page 18

    IS43/46DR86400B, IS43/46DR16320B Output Buffer Characteristics Output AC Test Conditions Symbol VOTR Output Timing Measurement Reference Level Note: The VDDQ of the device under test is referenced. Output DC Current Drive Symbol IOH(DC) Output Minimum Source DC Current IOL(DC) Output Minimum ...

  • Page 19

    IS43/46DR86400B, IS43/46DR16320B ODT DC Electrical Characteristics Parameter/Condition Rtt effective impedance value for EMRS(A6=0, A2=1); 75 ohm Rtt effective impedance value for EMRS(A6=1, A2=0); 150 ohm Rtt effective impedance value for EMRS(A6=A2=1); 50 ohm Deviation of VM with respect to VDDQ/2 ...

  • Page 20

    IS43/46DR86400B, IS43/46DR16320B IDD Specifications and Conditions IDD Measurement Conditions Symbol Parameter/Condition Operating Current - One bank Active - Precharge: IDD0 tRC = tRCmin; tCK =tCKmin ; Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS# = HIGH between ...

  • Page 21

    IS43/46DR86400B, IS43/46DR16320B IDD Specifications Symbol Configuration x8 IDD0 x16 x8 IDD1 x16 IDD2P x8/x16 x8 IDD2N x16 x8 IDD2Q x16 IDD3Pf x8/x16 IDD3Ps x8/x16 x8 IDD3N x16 x8 IDD4R x16 x8 IDD4W x16 IDD5B x8/x16 IDD6 x8/x16 x8 IDD7 x16 ...

  • Page 22

    IS43/46DR86400B, IS43/46DR16320B AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Row Actvie to Column Address Delay tRRD(x8) Row Active to Row Active Delay tRRD(x16) Column Address to ...

  • Page 23

    IS43/46DR86400B, IS43/46DR16320B AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol Data-In Hold Time to DQS-In (DQ, DM) DQS falling edge from CLK rising Setup Time DQS falling edge from CLK rising Hold Time DQ & DM Pulse Width ...

  • Page 24

    IS43/46DR86400B, IS43/46DR16320B AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol Average Periodic Refresh Interval (-40°C ≤ Tc ≤ +85°C) Average Periodic Refresh Interval (+85°C < Tc ≤ +95°C) Average Periodic Refresh Interval (+95°C < Tc ≤ +105°C) Period ...

  • Page 25

    IS43/46DR86400B, IS43/46DR16320B 14. User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-down mode” (MRS, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low ...

  • Page 26

    IS43/46DR86400B, IS43/46DR16320B Reference Loads, Slew Rates and Slew Rate Derating 1. Reference Load for Timing Measurements Figure AC Timing Reference Load represents the timing reference load used in defining the relevant timing parameters of the part not intended ...

  • Page 27

    ... IS43DR86400B-3DBL IS43DR16320B-3DBL 6-6-6 IS43DR16320B-25EBL 5-5-5 IS43DR16320B-25DBL = − 40°C to +85°C A CL-t -t Order Part No. RCD RP 4-4-4 IS43DR86400B-37CBLI IS43DR16320B-37CBLI 5-5-5 IS43DR86400B-3DBLI IS43DR16320B-3DBLI IS43DR16320B-3DBI 6-6-6 IS43DR86400B-25EBLI IS43DR16320B-25EBLI 5-5-5 IS43DR86400B-25DBLI IS43DR16320B-25DBLI = − 40°C to +85°C A CL-t -t Order Part No. RCD RP 4-4-4 IS46DR86400B-37CBLA1 IS46DR16320B-37CBLA1 5-5-5 IS46DR86400B-3DBLA1 ...

  • Page 28

    IS43/46DR86400B, IS43/46DR16320B PACKAGE OUTLINE DRAWING 60-ball FBGA: Fine Pitch Ball Grid Array Outline (x8) Integrated Silicon Solution, Inc. – www.issi.com – Rev. E, 01/17/2011 28 ...

  • Page 29

    IS43/46DR86400B, IS43/46DR16320B PACKAGE OUTLINE DRAWING 84-ball FBGA: Fine Pitch Ball Grid Array Outline (x16) Integrated Silicon Solution, Inc. – www.issi.com – Rev. E, 01/17/2011 29 ...