IS43DR16320B-3DBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16320B-3DBL Datasheet - Page 20

• Manufacturer Part Number: IS43DR16320B-3DBL
• Description: SDRAM, DDR2, 32M X 16, 1.8V, 84BGA
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS43DR16320B-3DBL

• Access Time: 0.45ns
• Page Size: 512Mbit
• Memory Case Style: BGA
• No. Of Pins: 84
• Operating Temperature Range: -40°C To +105°C
• Memory Type: SDRAM
• Memory Configuration: 4 BLK (8M X 16)
• Frequency: 333MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43/46DR86400B, IS43/46DR16320B
IDD Measurement Conditions
Notes:
1.
2.
3. Legend: A=Activate, RA=Read with Auto-Precharge, D=DESELECT.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. E, 01/17/2011
Symbol Parameter/Condition
IDD3Ps
IDD4W
IDD3Pf
IDD2N
IDD2Q
IDD3N
IDD2P
IDD4R
IDD5B
IDD0
IDD1
IDD6
IDD7
IDD Specifications and Conditions
Data Bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS and UDQS#.
Definitions for IDD :
Operating Current - One bank Active - Precharge:
tRC = tRCmin; tCK =tCKmin ; Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS# = HIGH between valid commands.
Operating Current - One bank Active - Read - Precharge:
One bank is accessed with tRCmin, BL = 4, tCK = tCKmin, AL = 0, CL = CLmin; Address bus and control inputs are SWITCHING,CS# = HIGH between valid
commands; lOUT = 0 mA.
Precharge Power-Down Current:
Precharge Standby Current:
All banks idle; CS# is HIGH; CKE is HIGH; tCK = tCKmin; Address bus, data bus, and control inputs are SWITCHING.
Precharge Quiet Standby Current:
All banks idle; CS# is HIGH; CKE is HIGH; tCK = tCKmin; Address bus and control inputs are STABLE; Data Bus inputs are FLOATING.
Active Power-Down Current:
All banks open; CKE is LOW; Address bus and control inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to “0”(Fast Power-down Exit).
Active Power-Down Current:
All banks open; CKE is LOW; Address bus and control inputs are STABLE; Data Bus inputs are FLOATING. MRS A12 bit is set to “1”(Slow Power-down Exit).
Active Standby Current:
All banks open; CS# is HIGH; CKE is HIGH; tRC = tRASmax; tCK = tCKmin; Address bus, data bus, and control inputs are SWITCHING.
Operating Current - Burst Read:
All banks active; continuous burst reads; BL = 4; AL = 0, CL = CLmin; tCK = tCKmin; Address bus, data bus, and control inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write:
All banks active; continuous burst writes; BL = 4; AL = 0, CL = CLmin; tCK = tCKmin; Address bus, data bus, and control inputs are SWITCHING; IOUT = 0mA.
Burst Auto-Refresh Current:
Refresh command at tRFC = tRFCmin, tCK = tCKmin, CS# is HIGH between valid commands.
Self-Refresh Current:
CKE 0.2V; external clock off, CK and CK# at 0V; tCK = tCKmin; Address bus, data bus, and control inputs, are FLOATING.
Operating Bank Interleave Read Current:
All bank interleaving with BL = 4; BL = 4, CL = CLmin; tRCD = tRCDmin; tRRD = tRRDmin; AL = tRCD - 1, IOUT = 0 mA. Address and control inputs are stable
during DESELECT; Data Bus inputs are SWITCHING.
a.
b.
c.
d.
e.
All banks idle; power-down mode; CKE is LOW; tCK = tCKmin; Data Bus inputs are FLOATING.
LOW is defined as V
HIGH is defined as V
STABLE is defined as inputs are stable at a HIGH or LOW level.
FLOATING is defined as inputs are VREF.
SWITCHING is defined as inputs are changing between HIGH and LOW every other clock for address and control signals, and inputs changing 50% of
each data transfer for DQ signals.
IN
IN
≤ V
≥ V
IL
IH
AC(Max).
AC(Min).
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