SST25VF080B-50-4I-S2AF SILICON STORAGE TECHNOLOGY, SST25VF080B-50-4I-S2AF Datasheet - Page 7

• Manufacturer Part Number: SST25VF080B-50-4I-S2AF
• Description: IC, FLASH, 8MBIT, 50MHZ, SOIC-8
• Manufacturer: SILICON STORAGE TECHNOLOGY

Specifications of SST25VF080B-50-4I-S2AF

• Memory Type: Flash
• Memory Size: 8Mbit
• Memory Configuration: 1M X 8
• Ic Interface Type: SPI
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8 Mbit SPI Serial Flash
SST25VF080B
Block Protection (BP3,BP2, BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
size of the memory area, as defined in Table 4, to be soft-
ware protected against any memory Write (Program or
Erase) operation. The Write-Status-Register (WRSR)
instruction is used to program the BP3, BP2, BP1 and BP0
bits as long as WP# is high or the Block-Protect-Lock
(BPL) bit is 0. Chip-Erase can only be executed if Block-
Protection bits are all 0. After power-up, BP3, BP2, BP1
and BP0 are set to 1.
TABLE 4: S
©2006 Silicon Storage Technology, Inc.
Protection Level
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
None
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
OFTWARE
S
TATUS
R
EGISTER
BP3
X
X
X
X
X
X
X
X
B
LOCK
Status Register Bit
P
ROTECTION FOR
BP2
0
0
0
0
1
1
1
1
7
Block Protection Lock-Down (BPL)
WP# pin driven low (V
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1, and BP0 bits.
When the WP# pin is driven high (V
effect and its value is “Don’t Care”. After power-up, the BPL
bit is reset to 0.
BP1
0
0
1
1
0
0
1
1
2
SST25VF080B
BP0
0
1
0
1
0
1
0
1
IL
1
), enables the Block-Protection-
Protected Memory Address
E0000H-FFFFFH
C0000H-FFFFFH
F0000H-FFFFFH
80000H-FFFFFH
00000H-FFFFFH
00000H-FFFFFH
00000H-FFFFFH
IH
8 Mbit
None
), the BPL bit has no
S71296-01-000
Data Sheet
T4.0 1296
1/06