PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet - Page 2

• Manufacturer Part Number: PIC24FJ256GB106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 51
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GB110 FAMILY
TABLE 2:
DS80369K-page 2
Core
Core
JTAG
UART
I/O
SPI
CTMU
USB
USB
USB
USB
UART
UART
UART
UART
UART
I
Module
I
Module
Memory
ICSP™
Core
RTCC
SPI
A/D
SPI
Core
CTMU
Oscillator
Oscillator
Output
Compare
Interrupts
A/D Converter
Note 1:
2
2
C™
C
Module
Only those issues indicated in the last column apply to the current silicon revision.
RAM Operation
BOR
Device
Programming
PORTB
Master mode
V
UERIF Interrupt
FIFO Error
IrDA
IrDA
IrDA
Master mode
Slave mode
PSV
Instruction Set
Enhanced Buffer
mode
Enhanced Buffer
mode
Code-Protect
A/D Trigger
LPRC
Two-Speed
Start-up
INTx
SILICON ISSUE SUMMARY
USB
Feature
®
Regulator
—
—
—
—
—
—
—
—
—
—
Number
Item
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Repeated register operations entering Doze mode
Programming lockout during JTAG programming
Framing issues when using two Stop bits
RB5 remains in high-impedance in Open-Drain mode
SPIxIF and SPIRBF may be set early in some
instances
Trigger to IC or OC modules may not work
Issue with Host mode, low-speed operation
Does not regulate to 3.3V
CRC errors while using external transceiver
cases
Payload error in 8-bit mode
Payload errors in 8-bit mode
Master module may Acknowledge its own transmission
as a slave
Module may not respond correctly to reserved
addresses
False address error traps
PGEC3/PGED3 not functional
Issue with Read-After-Write stalls in REPEAT loops
Unexpected decrements of Alarm Repeat Counter
Issue with early full buffer interrupt
Disabled voltage references during Debug mode
(64-pin devices only)
Issue with SRMPT bit becomes set early in certain
cases
GCP disables write access to interrupt vectors
Failure to restart following BOR events
Feature is not functional.
Single missed compare events under certain
conditions.
External interrupts missed when writing to INTCON2.
Module continues to draw current when disabled.
Spontaneous BOR with analog or USB peripherals
ACTIVIF flag functions only during Sleep
Interrupt may not function with multiple errors
PERR and FERR flags may be incorrect in certain
Framing error in 9-bit mode
Automatic conversion may not function
Issue Summary
 2010 Microchip Technology Inc.
Revisions
A3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
A5
X
X
X
X
X
X
X
X
X
X
(1)