PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet
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PIC24FJ256GB106-I/MR Summary of contents
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... PIC24FJ256GB110 Family © 2008 Microchip Technology Inc. Data Sheet 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) Preliminary DS39897B ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Interface for Off-Chip USB Transceiver • Supports Control, Interrupt, Isochronous and Bulk Transfers • On-Chip Pull-up and Pull-Down Resistors Device PIC24FJ64GB106 64 64K 16K PIC24FJ128GB106 64 128K 16K PIC24FJ192GB106 64 192K 16K PIC24FJ256GB106 64 256K 16K PIC24FJ64GB108 80 64K 16K PIC24FJ128GB108 80 128K 16K PIC24FJ192GB108 80 192K 16K ...
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... JTAG Boundary Scan and Programming Support • Brown-out Reset (BOR) • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Write protection option for Flash Configuration Words Preliminary © 2008 Microchip Technology Inc. ...
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... PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 PGEC3/RP18/V /C1INA/AN5/CN7/RB5 BUSON PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/V -/AN1/CN3/RB1 REF PGED1/RP0/PMA6/V +/AN0/CN2/RB0 REF Legend: RPn represents remappable pins for Peripheral Pin Select feature. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJXXXGB106 Preliminary RPI37/SOSCO/C3INC/TICK/ 48 CN0/RC14 47 ...
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... PGED1/RP0/AN0/CN2/RB0 20 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. DS39897B-page PIC24FJXXXGB108 Preliminary © 2008 Microchip Technology Inc. RPI37/SOSCO/C3INC/T1CK/CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/PMCS2/SCL1/CN55/RD10 RP4/DPLN/SDA1/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 RPI35/SDA2/CN44/RA15 RPI36/SCL2/CN43/RA14 V SS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 V DD D+/RG2 D-/RG3 V USB V BUS RP15/CN74/RF8 RP30/CN70/RF2 RP16/USBID/CN71/RF3 ...
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... TMS/CN33/RA0 17 RPI33/CN66/RE8 18 RPI34/CN67/RE9 19 PGEC3/RP18/V /C1INA/AN5/CN7/RB5 BUSON 20 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 21 VPIO/C2INA/AN3/CN5/RB3 22 VMIO/RP13/C2INB/AN2/CN4/RB2 23 PGEC1/RP1/AN1/CN3/RB1 24 PGED1/RP0/AN0/CN2/RB0 25 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJXXXGB110 Preliminary RPI37/SOSCO/C3INC/T1CK/ 74 CN0/RC14 73 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 72 RP12/PMCS1/CN56/RD11 71 RP3/PMCS2/CN55/RD10 70 RP4/DPLN/CN54/RD9 69 RP2/DMLN/RTCC/CN53/RD8 68 RPI35/SDA1/CN44/RA15 ...
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... Electrical Characteristics .......................................................................................................................................................... 293 29.0 Packaging Information.............................................................................................................................................................. 307 Appendix A: Revision History............................................................................................................................................................. 317 Index ................................................................................................................................................................................................. 319 The Microchip Web Site ..................................................................................................................................................................... 323 Customer Change Notification Service .............................................................................................................................................. 323 Customer Support .............................................................................................................................................................................. 323 Reader Response .............................................................................................................................................................................. 324 Product Identification System............................................................................................................................................................. 325 DS39897B-page 6 Preliminary © 2008 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 7 ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 8 Preliminary © 2008 Microchip Technology Inc. ...
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... This document contains device-specific information for the following devices: • PIC24FJ64GB106 • PIC24FJ192GB108 • PIC24FJ128GB106 • PIC24FJ256GB108 • PIC24FJ192GB106 • PIC24FJ64GB110 • PIC24FJ256GB106 • PIC24FJ128GB110 • PIC24FJ64GB108 • PIC24FJ192GB110 • PIC24FJ128GB108 • PIC24FJ256GB110 This expands on the existing line of Microchip‘s 16-bit microcontrollers, combining an expanded peripheral feature set and enhanced computational performance with a new connectivity option: USB On-The-Go ...
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... This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Preliminary memory (64 Kbytes for features available on the © 2008 Microchip Technology Inc. ...
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... JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) Instruction Set Packages Note 1: Peripherals are accessible through remappable pins. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 64GB106 128GB106 DC – 32 MHz 64K 128K 22,016 44,032 16,384 ...
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... Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 80-Pin TQFP Preliminary 256GB108 192K 256K 67,072 87,552 © 2008 Microchip Technology Inc. ...
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... JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) Instruction Set Packages Note 1: Peripherals are accessible through remappable pins. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 64GB110 128GB110 DC – 32 MHz 64K 128K 22,016 44,032 16,384 ...
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... MCLR 10-Bit (3) (3) RTCC Comparators ADC SPI UART I2C (3) (3) 1/2/3 1/2/3 1/2/3/4 Preliminary (1) PORTA 16 (13 I/O) PORTB (16 I/ (1) PORTC (8 I/ (1) PORTD (16 I/O) (1) PORTE (10 I/O) (1) PORTF 16-Bit ALU (9 I/O) 16 (1) PORTG (12 I/O) USB OTG PMP/PSP CTMU © 2008 Microchip Technology Inc. ...
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... C3INB 54 68 C3INC 48 60 C3IND 47 59 CLKI 39 49 CLKO 40 50 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP 25 I ANA A/D Analog Inputs ANA 23 I ANA 22 I ANA ...
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... CN39 — — CN40 — — CN41 — 23 CN42 — 24 Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 16 Input I/O Buffer TQFP Interrupt-on-Change Inputs Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... CN79 — — CN80 — — CN81 — — CN82 — — CTED1 28 34 CTED2 27 33 CTPLS REF Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP Interrupt-on-Change Inputs ...
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... O — — 71 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15 Parallel Master Port Chip Select 2 Strobe/Address Bit 14 — Parallel Master Port Byte Enable Strobe Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... RB13 28 34 RB14 29 35 RB15 30 36 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP 93 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). 94 I/O ...
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... I/O ST PORTD Digital I/ I/O ST PORTE Digital I/ I/O ST 100 — Reference Clock Output Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... RP14 29 35 RP15 — 43 RP16 33 41 RP17 32 40 RP18 11 15 RP19 6 8 Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP 87 I/O ST PORTF Digital I/ I/O ST ...
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... JTAG Test Data/Programming Data Input — JTAG Test Data Output JTAG Test Mode Select Input USB OTG ID (OTG mode only — USB Output Enable Control (for external transceiver Schmitt Trigger input buffer C™ C/SMBus input buffer Preliminary Description © 2008 Microchip Technology Inc. ...
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... REF V 9, 25, 41 11, 31, 51 15, 36, 45 USB Legend: TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP 54 P — USB Voltage, Host mode (5V — USB OTG External Charge Pump Control. ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 24 Preliminary © 2008 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... Control Signals to Various Blocks DS39897B-page 26 Data Bus 16 16 Data Latch PCL Data RAM Address Loop Latch Control Logic RAGU WAGU EA MUX ROM Latch 16 Instruction Reg Hardware Multiplier Register Array Divide Support 16-Bit ALU Preliminary Peripheral Modules © 2008 Microchip Technology Inc. ...
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... W10 W11 W12 W13 W14 W15 22 Registers or bits shadowed for PUSH.S and POP.S instructions. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register ...
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... Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39897B-page 28 U-0 U-0 — — (1) R-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,2) Preliminary U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. Description Preliminary © 2008 Microchip Technology Inc. ...
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... Device Config Registers Reserved DEVID (2) Note: Memory areas are not shown to scale. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Section 3.3 “Interfacing Program and Data Memory Spaces”. ...
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... Word for devices in the FLASH CONFIGURATION WORDS FOR PIC24FJ256GB110 FAMILY DEVICES Program Configuration Memory Word (Words) Addresses 00ABFAh: 22,016 00ABFEh 0157FAh: 44,032 0157FEh 020BFAh: 67,072 020BFEh 02ABFAh: 87,552 02ABFEh PC Address (LSW Address) 0 000000h 000002h 000004h 000006h © 2008 Microchip Technology Inc. ...
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... FFFFh Note: Data memory areas are not shown to scale. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJ256GB110 family devices implement a total of 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. ...
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... SPI — — — — — — — — CRC — System NVM/PMD — Preliminary xxA0 xxC0 xxE0 Interrupts — Compare UART I/O — — — USB — — — — PPS — — — — © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 35 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 36 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 37 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 38 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 39 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 40 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 41 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 42 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 43 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 44 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 45 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 46 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 47 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 48 Preliminary © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 49 ...
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... PIC24FJ256GB110 FAMILY DS39897B-page 50 Preliminary © 2008 Microchip Technology Inc. ...
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... W15 (before CALL) 000000000 PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... Bits 24 Bits Select 1 0 PSVPAG 8 Bits 23 Bits Preliminary <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 Bits Bits Byte Select © 2008 Microchip Technology Inc. ...
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... FIGURE 3-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...
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... PSV Area 800000h Preliminary 1111’ or 0000h Data EA<14:0> 8000h ...while the lower 15 bits of the EA specify an exact address within the PSV area. FFFFh This corresponds exactly to the same lower 15 bits of the actual program space address. © 2008 Microchip Technology Inc. ...
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... Using Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- tions (192 bytes time, and erase program memory in blocks of 512 instructions (1536 bytes time. Manual” ...
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... Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the opera- tion and the WR bit is automatically cleared when the operation is finished. Preliminary © 2008 Microchip Technology Inc. ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP3:NVMOP0 are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY (1) U-0 U-0 — — ...
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... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2008 Microchip Technology Inc. ...
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... W0 MOV W0, NVMKEY MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR BTSC NVMCON, #15 BRA $-2 © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY ; ; Initialize NVMCON ; ; Initialize PM Page Boundary SFR ; An example program memory address ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; ; ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; ; Set NVMOP bits to 0011 ; Disable interrupts while the KEY sequence is written ; Write the key sequence ; Start the write cycle Preliminary © 2008 Microchip Technology Inc. ...
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... Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...
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... SWDTEN bit setting. DS39897B-page 62 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... BOR MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Setting Event 5.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... OST LOCK T — RST T — RST T — RST T — RST T — RST T — RST PWRT Preliminary FSCM Notes Delay — FSCM FSCM FSCM — FSCM FSCM FSCM — 3 — 3 — 3 — 3 — 3 — 3 (64 ms nominal) if on-chip © 2008 Microchip Technology Inc. ...
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... FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 5.2.2.1 FSCM Delay for Crystal and PLL ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 66 Preliminary © 2008 Microchip Technology Inc. ...
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... PIC24FJ256GB110 family devices non-maskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...
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... Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 0001172h Reserved Preliminary (1) (1) Trap Source © 2008 Microchip Technology Inc. ...
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... Output Compare 6 Output Compare 7 Output Compare 8 Output Compare 9 Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Vector AIVT IVT Address Address 13 00002Eh 00012Eh 18 000038h 000138h ...
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... IEC0<3> IPC0<14:12> IEC0<7> IPC1<14:12> IEC0<8> IPC2<2:0> IEC1<11> IPC6<14:12> IEC1<12> IPC7<2:0> IEC4<1> IPC16<6:4> IEC0<11> IPC2<14:12> IEC0<12> IPC3<2:0> IEC4<2> IPC16<10:8> IEC1<14> IPC7<10:8> IEC1<15> IPC7<14:12> IEC5<1> IPC20<6:4> IEC5<2> IPC20<10:8> IEC5<3> IPC20<14:12> IEC5<7> IPC21<14:12> IEC5<8> IPC22<2:0> IEC5<9> IPC22<6:4> IEC5<6> IPC21<10:8> © 2008 Microchip Technology Inc. ...
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... See Register 2-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS39897B-page 72 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — ...
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... Interrupt request has not occurred DS39897B-page 74 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPF1IF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF ...
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... Interrupt request has not occurred DS39897B-page 76 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPF2IF bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — ...
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... Unimplemented: Read as ‘0’ DS39897B-page 78 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. U-0 R/W-0 — LVDIF bit 8 R/W-0 U-0 U1ERIF — bit Bit is unknown ...
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... Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 OC9IF SPI3IF SPF3IF ...
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... Interrupt request not enabled DS39897B-page 80 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPF1IE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 (1) ...
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... SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 “Peripheral Pin Select” for more information. DS39897B-page 82 Preliminary © 2008 Microchip Technology Inc. ...
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... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE ...
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... DS39897B-page 84 U-0 U-0 — — U-0 U-0 (1) — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 SI2C2IE — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 ...
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... Unimplemented: Read as ‘0’ DS39897B-page 86 R/W-0 R/W-0 R/W-0 OC9IE SPI3IE SPF3IE R/W-0 R/W-0 R/W-0 SI2C3IE U3TXIE U3RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U4TXIE U4RXIE bit 8 R/W-0 U-0 U3ERIE — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT0IP2:INT0IP0: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 ...
Page 90
... Unimplemented: Read as ‘0’ DS39897B-page 88 R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC2IP1 OC2IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 91
... Unimplemented: Read as ‘0’ bit 2-0 T3IP2:T3IP0: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 ...
Page 92
... Interrupt source is disabled DS39897B-page 90 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — U1TXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 U1TXIP1 U1TXIP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 2-0 SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 ...
Page 94
... Interrupt source is disabled DS39897B-page 92 R/W-0 U-0 R/W-1 IC8IP0 — IC7IP2 U-0 U-0 R/W-1 — — INT1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC7IP1 IC7IP0 bit 8 R/W-0 R/W-0 INT1IP1 INT1IP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 95
... OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 ...
Page 96
... Interrupt source is disabled DS39897B-page 94 R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — T5IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2RXIP1 U2RXIP0 bit 8 R/W-0 R/W-0 T5IP1 T5IP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 97
... Unimplemented: Read as ‘0’ bit 2-0 SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 98
... Unimplemented: Read as ‘0’ DS39897B-page 96 R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC4IP1 IC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 99
... Unimplemented: Read as ‘0’ bit 2-0 IC6IP2:IC6IP0: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 OC7IP0 — OC6IP2 R/W-0 ...
Page 100
... Interrupt source is disabled DS39897B-page 98 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 PMPIP0 — OC8IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 OC8IP1 OC8IP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 101
... SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 R/W-1 — — MI2C2P2 R/W-0 ...
Page 102
... DS39897B-page 100 U-0 U-0 R/W-1 — — INT4IP2 R/W-0 U-0 U-0 INT3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 INT4IP1 INT4IP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 103
... RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 ...
Page 104
... DS39897B-page 102 R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2ERIP1 U2ERIP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 105
... CTMUIP2:CTMUIP0: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 106
... DS39897B-page 104 R/W-0 U-0 R/W-1 U3TXIP0 — U3RXIP2 R/W-0 U-0 U-0 U3ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U3RXIP1 U3RXIP0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 107
... Unimplemented: Read as ‘0’ bit 2-0 SI2C3P2:SI2C3P0: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 R/W-0 R/W-1 U4ERIP0 — USB1IP2 R/W-0 ...
Page 108
... DS39897B-page 106 R/W-0 U-0 R/W-1 SPI3IP0 — SPF3IP2 R/W-0 U-0 R/W-1 U4TXIP0 — U4RXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPF3IP1 SPF3IP0 bit 8 R/W-0 R/W-0 U4RXIP1 U4RXIP0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 109
... Unimplemented: Read as ‘0’ bit 2-0 OC9IP2:OC9IP0: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 110
... Note that only user interrupts with a priority level less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. Preliminary © 2008 Microchip Technology Inc. ...
Page 111
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY • An on-chip USB PLL block to provide a stable 48 MHz clock for the USB module as well as a range of frequency options for the system clock • Software-controllable switching between various clock sources • ...
Page 112
... Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 Preliminary the program memory (refer to “Configuration Bits” for further (Configuration Word 2<10:8>), Configuration bits (Configuration FNOSC2: Note FNOSC0 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000 © 2008 Microchip Technology Inc. ...
Page 113
... IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY The OSCCON register (Register 7-1) is the main con- trol register for the oscillator ...
Page 114
... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL clock mode is selected. DS39897B-page 112 (2) (3) Preliminary © 2008 Microchip Technology Inc. ...
Page 115
... MHz (divide by 1) bit 5-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2: This setting is not allowed while the USB module is enabled. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 ...
Page 116
... Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled held at ‘0’ at all times. Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 117
... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence ...
Page 118
... HSPLL, ECPLL ÷4 (011) HSPLL, ECPLL ÷3 (010) HSPLL, ECPLL ÷2 (001) HSPLL, ECPLL ÷1 (000) HSPLL, ECPLL, XTPLL 48 MHz Clock for USB Module ÷ PLL Output ÷ 4 for System Clock 10 ÷ ÷ CPDIV1:CPDIV0 © 2008 Microchip Technology Inc. ...
Page 119
... They may still be useful in cases where other power levels of operation are desirable and the USB module is not needed (e.g., the application is sleeping and waiting for bus attachment). © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.6 Reference Clock Output In addition to the CLKO output (F ...
Page 120
... DS39897B-page 118 R/W-0 R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RODIV1 RODIV0 bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 121
... Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes said to “ ...
Page 122
... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows possible further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications. Preliminary © 2008 Microchip Technology Inc. ...
Page 123
... CK WR PORT Data Latch Read LAT Read PORT © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY peripheral that shares the same pin. Figure 9-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled ...
Page 124
... Make sure that there is no external DD pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. Preliminary © 2008 Microchip Technology Inc. ...
Page 125
... RPI32 to RPI43 (or the upper limit for that particular device). See Table 1-4 for a summary of pinout options in each package offering. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 9.4.2 AVAILABLE PERIPHERALS The peripherals managed by the peripheral pin select are all digital only peripherals ...
Page 126
... INT2R5:INT2R0 INT3R5:INT3R0 INT4R5:INT4R0 IC1R5:IC1R0 IC2R5:IC2R0 IC3R5:IC3R0 IC4R5:IC4R0 IC5R5:IC5R0 IC6R5:IC6R0 IC7R5:IC7R0 IC8R5:IC8R0 IC9R5:IC9R0 OCFAR5:OCFAR0 OCFBR5:OCFBR0 SCK1R5:SCK1R0 SDI1R5:SDI1R0 SS1R5:SS1R0 SCK2R5:SCK2R0 SDI2R5:SDI2R0 SS2R5:SS2R0 SCK3R5:SCK3R0 SDI3R5:SDI3R0 SS3R5:SS3R0 T1CKR5:T1CKR0 T2CKR5:T2CKR0 T3CKR5:T3CKR0 T4CKR5:T4CKR0 T5CKR5:T5CKR0 U1CTSR5:U1CTSR0 U1RXR5:U1RXR0 U2CTSR5:U2CTSR0 U2RXR5:U2RXR0 U3CTSR5:U3CTSR0 U3RXR5:U3RXR0 U4CTSR5:U4CTSR0 U4RXR5:U4RXR0 © 2008 Microchip Technology Inc. ...
Page 127
... The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. ® 3: IrDA BCLK functionality uses this output. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 9-2). ...
Page 128
... IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. RP Pins (I/O) Unimplemented Total RP5, RP15, RP30, RP31 1 RP31 9 — 12 Preliminary RPI Pins Unimplemented RPI32-36, RPI38-43 RPI32, RPI39, RPI41 — © 2008 Microchip Technology Inc. ...
Page 129
... To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that fea- ture on ...
Page 130
... INT2R3 INT2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 INT1R1 INT1R0 bit 8 U-0 U-0 — — bit Bit is unknown R/W-1 R/W-1 INT3R1 INT3R0 bit 8 R/W-1 R/W-1 INT2R1 INT2R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 131
... T3CKR5:T3CKR0: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR5:T2CKR0: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 T1CKR4 ...
Page 132
... IC1R3 IC1R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 T5CKR1 T5CKR0 bit 8 R/W-1 R/W-1 T4CKR1 T4CKR0 bit Bit is unknown R/W-1 R/W-1 IC2R1 IC2R0 bit 8 R/W-1 R/W-1 IC1R1 IC1R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 133
... IC6R5:IC6R0: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC5R5:IC5R0: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 IC4R4 ...
Page 134
... OCFAR3 OCFAR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 IC8R1 IC8R0 bit 8 R/W-1 R/W-1 IC7R1 IC7R0 bit Bit is unknown R/W-1 R/W-1 OCFBR1 OCFBR0 bit 8 R/W-1 R/W-1 OCFAR1 OCFAR0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 135
... Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3RXR5:U3RXR0: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 IC9R4 IC9R3 IC9R2 ...
Page 136
... U2RXR3 U2RXR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 U1CTSR1 U1CTSR0 bit 8 R/W-1 R/W-1 U1RXR1 U1RXR0 bit Bit is unknown R/W-1 R/W-1 U2CTSR1 U2CTSR0 bit 8 R/W-1 R/W-1 U2RXR1 U2RXR0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 137
... U3CTSR5:U3CTSR0: Assign UART3 Clear to Send (U3CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R5:SS1R0: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 ...
Page 138
... SS2R3 SS2R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 SCK2R1 SCK2R0 bit 8 R/W-1 R/W-1 SDI2R1 SDI2R0 bit Bit is unknown U-0 U-0 — — bit 8 R/W-1 R/W-1 SS2R1 SS2R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 139
... SCK3R5:SCK3R0: Assign SPI3 Clock Input (SCK3IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI3R5:SDI3R0: Assign SPI3 Data Input (SDI3) to Corresponding RPn or RPIn Pin bits © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 U4CTSR4 ...
Page 140
... RP0R3 RP0R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-1 R/W-1 SS3R1 SS3R0 bit Bit is unknown R/W-0 R/W-0 RP1R1 RP1R0 bit 8 R/W-0 R/W-0 RP0R1 RP0R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 141
... Unimplemented: Read as ‘0’ bit 5-0 RP4R5:RP4R0: RP4 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP4 (see Table 9-2 for peripheral function numbers) Note 1: Unimplemented in 64-pin devices; read as ‘0’. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 RP3R4 RP3R3 ...
Page 142
... RP8R3 RP8R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP7R1 RP7R0 bit 8 R/W-0 R/W-0 RP6R1 RP6R0 bit Bit is unknown R/W-0 R/W-0 RP9R1 RP9R0 bit 8 R/W-0 R/W-0 RP8R1 RP8R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 143
... Peripheral Output number n is assigned to pin RP13 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP12R5:RP12R0: RP12 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP12 (see Table 9-2 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP11R4 ...
Page 144
... RP16R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 (1) (1) (1) RP15R1 RP15R0 bit 8 R/W-0 R/W-0 RP14R1 RP14R0 bit Bit is unknown R/W-0 R/W-0 RP17R1 RP17R0 bit 8 R/W-0 R/W-0 RP16R1 RP16R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 145
... Peripheral Output number n is assigned to pin RP21 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP20R5:RP20R0: RP20 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP20 (see Table 9-2 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP19R4 ...
Page 146
... RP24R3 RP24R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RP23R1 RP23R0 bit 8 R/W-0 R/W-0 RP22R1 RP22R0 bit Bit is unknown R/W-0 R/W-0 RP25R1 RP25R0 bit 8 R/W-0 R/W-0 RP24R1 RP24R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 147
... Peripheral Output number n is assigned to pin RP29 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP28R5:RP28R0: RP28 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP28 (see Table 9-2 for peripheral function numbers) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP27R4 ...
Page 148
... RP31R4 RP31R3 RP31R2 R/W-0 R/W-0 R/W-0 (2) (2) (2) RP30R4 RP30R3 RP30R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 (1) (1) (1) RP31R1 RP31R0 bit 8 R/W-0 R/W-0 (2) (2) (2) RP30R1 RP30R0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 149
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. ...
Page 150
... DS39897B-page 148 (1) U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 151
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). ...
Page 152
... The ADC Event Trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS39897B-page 150 1x Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR2 TMR3 (TMR4) (TMR5 TMR3HLD (TMR5HLD) Preliminary TCKPS1:TCKPS0 2 TON Prescaler 1, 8, 64, 256 (2) TGATE (2) TCS Sync © 2008 Microchip Technology Inc. ...
Page 153
... Equal Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. 2: The ADC Event Trigger is available only on Timer3. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 1x Gate Sync 01 ...
Page 154
... DS39897B-page 152 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /2) Preliminary (3) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (2) — TCS — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 155
... If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 (1) — ...
Page 156
... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 154 Preliminary © 2008 Microchip Technology Inc. ...
Page 157
... Reset Trigger and Sync Sources Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 12.1 General Operating Modes 12.1.1 SYNCHRONOUS AND TRIGGER ...
Page 158
... ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (perform automatically by hardware). Preliminary © 2008 Microchip Technology Inc. for both modules configure Trigger ...
Page 159
... Input capture module turned off Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 9.4 “Peripheral Pin Select”. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 ICTSEL2 ...
Page 160
... R/W-0 R/W-0 SYNCSEL4 SYNCSEL3 SYNCSEL2 HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) Preliminary U-0 U-0 R/W-0 — — IC32 bit 8 R/W-0 R/W-0 R/W-0 SYNCSEL1 SYNCSEL0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 161
... Compare or PWM events are generated each time a match between the internal counter and one of the period registers occurs. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module’ ...
Page 162
... Pin Select” for more information. DS39897B-page 160 OCxCON1 OCxCON2 OCxR Match Event Comparator OCxTMR Reset Match Event Comparator OCxRS Preliminary OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 (1) OCx Pin OC Output and Fault Logic OCFA/OCFB OCx Interrupt © 2008 Microchip Technology Inc. ...
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... TON bit for the selected timer which enables the compare time base to count. Synchronous mode operation starts as soon as the time base is enabled; Trigger mode operation starts after a trigger source event occurs. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY For 32-bit cascaded operation, these steps are also necessary: 1. ...
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... Rollover Reset Comparator Match Event OCxRS buffer Rollover/Reset OCxRS Preliminary clock source by writing the the peripheral pin select. See OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 OCx Pin OC Output and Fault Logic OCFA/OCFB OCx Interrupt © 2008 Microchip Technology Inc. ...
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... Note 1: Based Doze mode and PLL are disabled. CY OSC © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 13.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i ...
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... DS39897B-page 164 61 Hz 122 Hz 977 Hz 3.9 kHz FFFFh 7FFFh 0FFFh 03FFh 244 Hz 488 Hz 3.9 kHz 15.6 kHz FFFFh 7FFFh 0FFFh 03FFh Preliminary ( MHz) CY 31.3 kHz 125 kHz 007Fh 001Fh ( MHz) CY 125 kHz 500 kHz 007Fh 001Fh © 2008 Microchip Technology Inc. ...
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... The OCx output must also be configured to an available RPn pin. For more information, see Section 9.4 “Peripheral Pin Select”. 2: OCFA pin controls OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and OCxRS are double-buffered only in PWM modes. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 ...
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... DS39897B-page 166 R/W-0 U-0 U-0 OCINV — — R/W-0 R/W-0 R/W-0 SYNCSEL4 SYNCSEL3 SYNCSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 OC32 — bit 8 R/W-0 R/W-0 SYNCSEL1 SYNCSEL0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Not synchronized to any other module Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY (1) (2) (2) (2) ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 168 Preliminary © 2008 Microchip Technology Inc. ...
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... Enhanced Buffer mode. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY The SPI serial interface consists of four pins: • SDIx: Serial Data Input • ...
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... Clear the SPIROV bit (SPIxSTAT<6>). 7. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPIxBUF 16 Internal Data Bus Preliminary registers with MSTEN 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2008 Microchip Technology Inc. ...
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... SDOx bit0 SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: a) Clear the SPIxIF bit in the respective IFS register ...
Page 174
... DS39897B-page 172 U-0 U-0 — — SPIBEC2 R/W-0 R/W-0 SISEL2 SISEL1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-0 R-0 R-0 SPIBEC1 SPIBEC0 bit 8 R/W-0 R-0 R-0 SISEL0 SPITBF SPIRBF bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 173 ...
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... R/W-0 R/W-0 (1) (2) DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) Preliminary R/W-0 R/W-0 (3) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — ...
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... SDIx SDOx Serial Clock SCKx SCKx SSx SSx SSEN (SPIxCON1<7> MSTEN (SPIxCON1<5> and SPIBEN (SPIxCON2<0> Preliminary (SPIxRXB) Shift Register (SPIxSR) LSb (SPIxTXB) SPIx Buffer (SPIxBUF) Shift Register (SPIxSR) MSb LSb 8-Level FIFO Buffer SPIx Buffer (SPIxBUF) © 2008 Microchip Technology Inc. ...
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... FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 14-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Master, Frame Slave) © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx ...
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... Preliminary (1) 4:1 6:1 8:1 4000 2667 2000 1000 667 500 250 167 125 1250 833 625 313 208 156 © 2008 Microchip Technology Inc. ...
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... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 15-1. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 15.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
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... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2008 Microchip Technology Inc. ...
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... The address bits listed here will never cause an address match, independent of address mask settings. 2: Address will be Acknowledged only if GCEN = 1. 3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 15.3 Slave Address Masking The I2CxMSK register (Register 15-3) designates address bit positions as “ ...
Page 184
... R/W-0, HC R/W-0, HC ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C pins are controlled by port functions Slave slave slave) Preliminary R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Repeated Start condition not in progress bit 0 SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2 C master. Applicable during master receive master ...
Page 186
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C slave) Preliminary R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit 0 HSC = Hardware Settable/ Clearable bit x = Bit is unknown 2 C module is busy © 2008 Microchip Technology Inc. ...
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... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2 C slave device address byte. ...
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... DS39897B-page 186 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 AMSK4 AMSK3 AMSK2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 189
... Note: The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • ...
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... Preliminary /(16 * 65536). UART BAUD RATE WITH (1,2) BRGH = • (UxBRG + – • Baud Rate denotes the instruction cycle clock = F /2, Doze mode CY OSC /4 CY (1) © 2008 Microchip Technology Inc. ...
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... Write ‘55h’ to UxTXREG; this loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.5 Receiving in 8-Bit or 9-Bit Data Mode 1. ...
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... U-0 (2) IREN RTSMD — R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R/W-0 R/W-0 UEN1 UEN0 bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. 2: This feature is only available for the 16x BRG mode (BRGH = 0). © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 191 ...
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... R/W-0 — UTXBRK UTXEN R-1 R-0 R-0 RIDLE PERR FERR HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Preliminary R-0 R-1 (2) UTXBF TRMT bit 8 R/C-0 R-0 OERR URXDA bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1 UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Preliminary DS39897B-page 193 ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 194 Preliminary © 2008 Microchip Technology Inc. ...
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... Configurations for on-chip bus pull-up and pull-down resistors A simplified block diagram of the USB OTG module is shown in Figure 17-1. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY The USB OTG module can function as a USB periph- eral device USB host, and may dynamically switch between Device and Host modes under soft- ware control ...
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... Pins are multiplexed with digital I/O and other device features. DS39897B-page 196 Transceiver Host Pull-down USB SIE External Transceiver Interface USB Voltage Comparators USB 3.3V Regulator V BUS Boost Assist Preliminary 48 MHz USB Clock Registers and Control Interface System RAM © 2008 Microchip Technology Inc. ...
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... Descriptor EP15 Tx Descriptor Note: Memory area not shown to scale. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Depending on the endpoint buffering configuration used, there are sets of buffer descriptors, for a total of 256 bytes minimum, the BDT must be at least 8 bytes long. This is because the USB specifica- tion mandates that every device must have Endpoint 0 with both input and output for initial setup ...
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... R/W-x R/W-x R/W-x PID2 PID1 PID0 R/W-x R/W-x R/W-x BC4 BC3 BC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-x BC9 BC8 bit 8 R/W-x R/W-x BC1 BC0 bit Bit is unknown © 2008 Microchip Technology Inc. ...