PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet - Page 205

• Manufacturer Part Number: PIC24FJ256GB106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 51
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.
7.
8.
9.
10. Perform enumeration as described by Chapter 9
17.5.2
1.
2.
3.
4.
5.
6.
© 2008 Microchip Technology Inc.
Check the state of the JSTATE and SE0 bits in
U1CON. If the JSTATE bit (U1CON<7>) is ‘0’,
the connecting device is low speed. If the con-
necting device is low speed, set the low
LSPDEN and LSPD bits (U1ADDR<7> and
U1EP0<7>) to enable low-speed operation.
Reset the USB device by setting the RESET bit
(U1CON<4>) for at least 50 ms, sending Reset
signaling on the bus. After 50 ms, terminate the
Reset by clearing RESET.
To keep the connected device from going into
suspend, enable SOF packet generation to keep
by setting the SOFEN bit.
Wait 10 ms for the device to recover from Reset.
of the USB 2.0 specification.
Follow
Section 17.5.1 “Enable Host Mode and Dis-
cover a Connected Device” to discover a
device.
Set up the Endpoint Control register for
bidirectional control transfers by writing 0Dh to
U1EP0 (this sets the EPCONDIS, EPTXEN, and
EPHSHK bits).
Place a copy of the device framework setup
command in a memory buffer. See Chapter 9 of
the USB 2.0 specification for information on the
device framework command set.
Initialize the buffer descriptor (BD) for the
current (EVEN or ODD) Tx EP0, to transfer the
eight bytes of command data for a device
framework command (i.e., a GET DEVICE
DESCRIPTOR):
a)
b)
Set the USB device address of the target device
in the address register (U1ADDR<6:0>). After a
USB bus Reset, the device USB address will be
zero. After enumeration, it will be set to another
value between 1 and 127.
Write D0h to U1TOK; this is a SETUP token to
Endpoint 0, the target device’s default control
pipe. This initiates a SETUP token on the bus, fol-
lowed by a data packet. The device handshake is
returned in the PID field of BD0STAT after the
packets are complete. When the USB module
updates BD0STAT, a transfer done interrupt is
asserted (the TRNIF flag is set). This completes
the setup phase of the setup transaction as
referenced in chapter 9 of the USB specification.
Set the BD data buffer address (BD0ADR)
to the starting address of the 8-byte
memory buffer containing the command.
Write 8008h to BD0STAT (this sets the
UOWN bit, and sets a byte count of 8).
COMPLETE A CONTROL
TRANSACTION TO A CONNECTED
DEVICE
the
procedure
described
PIC24FJ256GB110 FAMILY
in
Preliminary
7.
8.
9.
10. To initiate the status phase of the setup transac-
11. Initialize the current (even or odd) Tx EP0 BD to
12. Write the Token register with the appropriate IN
Note:
To initiate the data phase of the setup transac-
tion (i.e., get the data for the GET DEVICE
descriptor command), set up a buffer in memory
to store the received data.
Initialize the current (EVEN or ODD) Rx or Tx
(Rx for IN, Tx for OUT) EP0 BD to transfer the
data.
a)
b)
Write the token register with the appropriate IN
or OUT token to Endpoint 0, the target device’s
default control pipe (e.g., write 90h to U1TOK for
an IN token for a GET DEVICE DESCRIPTOR
command). This initiates an IN token on the bus
followed by a data packet from the device to the
host. When the data packet completes, the
BD0STAT is written and a transfer done interrupt
is asserted (the TRNIF flag is set). For control
transfers with a single packet data phase, this
completes the data phase of the setup transac-
tion as referenced in chapter 9 of the USB
specification. If more data needs to be
transferred, return to step 8.
tion, set up a buffer in memory to receive or send
the zero length status phase data packet.
transfer the status data.:
a)
b)
or OUT token to Endpoint 0, the target device’s
default control pipe (e.g., write 01h to U1TOK for
an OUT token for a GET DEVICE DESCRIP-
TOR command). This initiates an OUT token on
the bus followed by a zero length data packet
from the host to the device. When the data
packet completes, the BD is updated with the
handshake from the device, and a transfer done
interrupt is asserted (the TRNIF flag is set). This
completes the status phase of the setup trans-
action as described in chapter 9 of the USB
specification.
Write C040h to BD0STAT. This sets the
UOWN, configures Data Toggle (DTS) to
DATA1, and sets the byte count to the
length of the data buffer (64 or 40h, in this
case).
Set BD0ADR to the starting address of the
data buffer.
Set the BDT buffer address field to the start
address of the data buffer
Write 8000h to BD0STAT (set UOWN bit,
configure DTS to DATA0, and set byte
count to 0).
Only one control transaction can be
performed per frame.
DS39897B-page 203