PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet - Page 158

• Manufacturer Part Number: PIC24FJ256GB106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 51
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GB110 FAMILY
12.1.2
By default, each module operates independently with
its own 16-bit timer. To increase resolution, adjacent
even and odd modules can be configured to function as
a single 32-bit module. (For example, modules 1 and 2
are paired, as are modules 3 and 4, and so on.) The
odd-numbered module (ICx) provides the Least Signif-
icant 16 bits of the 32-bit register pairs, and the even
module (ICy) provides the Most Significant 16 bits.
Wraparounds of the ICx registers cause an increment
of their corresponding ICy registers.
Cascaded operation is configured in hardware by
setting the IC32 bits (ICxCON2<8>) for both modules.
12.2
The input capture module can be configured to capture
timer values and generate interrupts on rising edges on
ICx, or all transitions on ICx. Captures can be configured
to occur on all rising edges, or just some (every 4th or
16th). Interrupts can be independently configured to
generate on each event, or a subset of events.
To set up the module for capture operations:
1.
2.
3.
4.
5.
6.
7.
8.
9.
DS39897B-page 156
Configure the ICx input for one of the available
peripheral pin select pins.
If Synchronous mode is to be used, disable the
sync source before proceeding.
Make sure that any previous data has been
removed from the FIFO by reading ICxBUF until
the ICBNE bit (ICxCON1<3>) is cleared.
Set the SYNCSEL bits (ICxCON2<4:0>) to the
desired sync/trigger source.
Set the ICTSEL bits (ICxCON1<12:10>) for the
desired clock source.
Set the ICI bits (ICxCON1<6:5>) to the desired
interrupt frequency
Select Synchronous or Trigger mode operation:
a)
b)
c)
Set the ICM bits (ICxCON1<2:0>) to the desired
operational mode.
Enable the selected trigger/sync source.
Capture Operations
Check that the SYNCSEL bits are not set to
‘00000’.
For Synchronous mode, clear the ICTRIG
bit (ICxCON2<7>).
For Trigger mode, set ICTRIG, and clear the
TRIGSTAT bit (ICxCON2<6>).
CASCADED (32-BIT) MODE
Preliminary
For 32-bit cascaded operations, the setup procedure is
slightly different:
1.
2.
3.
4.
5.
6.
The module is ready to capture events when the time
base and the trigger/sync source are enabled. When
the ICBNE bit (ICxCON1<3>) becomes set, at least
one capture value is available in the FIFO. Read input
capture values from the FIFO until the ICBNE clears to
‘0’.
For 32-bit operation, read both the ICxBUF and
ICyBUF for the full 32-bit timer value (ICxBUF for the
lsw, ICyBUF for the msw). At least one capture value is
available in the FIFO buffer when the odd module’s
ICBNE bit (ICxCON1<3>) becomes set. Continue to
read the buffer registers until ICBNE is cleared
(perform automatically by hardware).
Note:
Set
(ICyCON2<8> and (ICxCON2<8>), enabling the
even-numbered module first. This ensures the
modules will start functioning in unison.
Set the ICTSEL and SYNCSEL bits for both
modules to select the same sync/trigger and
time base source. Set the even module first,
then the odd module. Both modules must use
the same ICTSEL and SYNCSEL settings.
Clear the ICTRIG bit of the even module
(ICyCON2<7>); this forces the module to run in
Synchronous mode with the odd module,
regardless of its trigger setting.
Use the odd module’s ICI bits (ICxCON1<6:5>)
to the desired interrupt frequency.
Use the ICTRIG bit of the odd module
(ICxCON2<7>)
Synchronous mode operation.
Use the ICM bits of the odd module
(ICxCON1<2:0>) to set the desired capture
mode.
the
For Synchronous mode operation, enable
the sync source as the last step. Both
input capture modules are held in Reset
until the sync source is enabled.
IC32
to
© 2008 Microchip Technology Inc.
bits
configure
for
both
Trigger
modules
or