PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet - Page 248

• Manufacturer Part Number: PIC24FJ256GB106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 51
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GB110 FAMILY
FIGURE 20-2:
20.1
20.1.1
To start serial shifting, a ‘1’ must be written to the
CRCGO bit.
The module incorporates a FIFO that is 8 deep when
the value of the PLEN bits (CRCCON<3:0>) > 7, and
16 deep, otherwise. The data for which the CRC is to
be calculated must first be written into the FIFO. The
smallest data element that can be written into the FIFO
is one byte. For example, if PLEN = 5, then the size of
the data is PLEN + 1 = 6. The data must be written as
follows:
Once data is written into the CRCWDAT MSb (as
defined by PLEN), the value of the VWORD bits
(CRCCON<12:8>) increments by one. The serial
shifter starts shifting data into the CRC engine when
CRCGO = 1 and VWORD > 0. When the MSb is
shifted out, VWORD decrements by one. The serial
shifter continues shifting until the VWORD reaches 0.
Therefore, for a given value of PLEN, it will take
(PLEN + 1) * VWORD number of clock cycles to
complete the CRC calculations.
When VWORD reaches 8 (or 16), the CRCFUL bit will
be set. When VWORD reaches 0, the CRCMPT bit will
be set.
To continually feed data into the CRC engine, the rec-
ommended mode of operation is to initially “prime” the
FIFO with a sufficient number of words so no interrupt
is generated before the next word can be written. Once
that is done, start the CRC by setting the CRCGO bit to
‘1’. From that point onward, the VWORD bits should be
polled. If they read less than 8 or 16, another word can
be written into the FIFO.
DS39897B-page 246
SDOx
XOR
User Interface
DATA INTERFACE
D
data[5:0] = crc_input[5:0]
BIT 0
p_clk
Q
data[7:6] = ‘bxx
CRC GENERATOR RECONFIGURED FOR x
D
p_clk
BIT 4
Q
Preliminary
D
BIT 5
p_clk
Q
To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the
VWORD Pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the con-
dition to generate an interrupt will not be met; therefore,
no interrupt will be generated (See Section 20.1.2
“Interrupt Operation”).
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
20.1.2
When the VWORD4:VWORD0 bits make a transition
from a value of ‘1’ to ‘0’, an interrupt will be generated.
20.2
20.2.1
If Sleep mode is entered while the module is operating,
the module will be suspended in its current state until
clock execution resumes.
20.2.2
To continue full module operation in Idle mode, the
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode; pending interrupt events will be
passed on, even though the module clocks are not
available.
Operation in Power Save Modes
16
INTERRUPT OPERATION
SLEEP MODE
IDLE MODE
+ x
12
CRC Read Bus
D
BIT 12
p_clk
+ x
Q
5
© 2008 Microchip Technology Inc.
+ 1
CRC Write Bus
BIT 15
D
p_clk
Q