PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet
PIC24FJ256GB106-I/MR
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PIC24FJ256GB106-I/MR Summary of contents
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... PIC24FJ256GB110 Family 2009 Microchip Technology Inc. Data Sheet 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) DS39897C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Interface for Off-Chip USB Transceiver • Supports Control, Interrupt, Isochronous and Bulk Transfers • On-Chip Pull-up and Pull-Down Resistors Device PIC24FJ64GB106 64 64K 16K PIC24FJ128GB106 64 128K 16K PIC24FJ192GB106 64 192K 16K PIC24FJ256GB106 64 256K 16K PIC24FJ64GB108 80 64K 16K PIC24FJ128GB108 80 128K 16K PIC24FJ192GB108 80 192K 16K ...
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... In-Circuit Debug (ICD) via 2 Pins • JTAG Boundary Scan and Programming Support • Brown-out Reset (BOR) • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Write protection option for Flash Configuration Words 2009 Microchip Technology Inc. ...
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... RPn represents remappable pins for the Peripheral Pin Select feature. Note 1: For QFN devices, the backplane on the underside of the device must also be connected to V 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJ64GB106 7 PIC24FJ128GB106 8 PIC24FJ192GB106 9 SS PIC24FJ256GB106 SOSCO/T1CK/C3INC/RPI37/ 48 CN0/RC14 47 SOSCI/C3IND/CN1/RC13 46 DMH/RP11/INT0/CN49/RD0 45 RP12/PMCS1/CN56/RD11 44 SCL1/RP3/PMCS2/CN55/RD10 ...
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... RPn represents remappable pins for the Peripheral Pin Select feature. DS39897C-page 6 60 SOSCO/T1CK/C3INC/RPI37/CN0/RC14 59 SOSCI/C3IND/CN1/RC13 58 DMH/RP11/INT0/CN49/RD0 57 RP12/PMCS1/CN56/RD11 56 SCL1/RP3/PMCS2/CN55/RD10 55 SDA1/DPLN/RP4/CN54/RD9 54 DMLN/RTCC/RP2/CN53/RD8 53 SDA2/RPI35/CN44/RA15 PIC24FJ64GB108 52 SCL2/RPI36/CN43/RA14 PIC24FJ128GB108 51 V PIC24FJ192GB108 OSCO/CLKO/CN22/RC15 50 PIC24FJ256GB108 49 OSCI/CLKI/CN23/RC12 D+/RG2 46 D-/RG3 RP15/CN74/RF8 43 RP30/CN70/RF2 42 41 RP16/USBID/CN71/RF3 2009 Microchip Technology Inc USB BUS ...
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... BUSON 20 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 21 AN3/C2INA/VPIO/CN5/RB3 22 AN2/C2INB/VMIO/RP13/CN4/RB2 23 PGEC1/AN1/RP1/CN3/RB1 24 PGED1/AN0/RP0/CN2/RB0 25 Legend: Shaded pins indicate pins tolerant +5.5 VDC. RPn and RPIn represent remappable pins for the Peripheral Pin Select features. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJ64GB110 PIC24FJ128GB110 PIC24FJ192GB110 PIC24FJ256GB110 SOSCO/T1CK/C3INC/RPI37/ 74 CN0/RC14 73 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 ...
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... Instruction Set Summary .......................................................................................................................................................... 303 29.0 Electrical Characteristics .......................................................................................................................................................... 311 30.0 Packaging Information.............................................................................................................................................................. 327 Appendix A: Revision History............................................................................................................................................................. 341 Index ................................................................................................................................................................................................. 343 The Microchip Web Site ..................................................................................................................................................................... 349 Customer Change Notification Service .............................................................................................................................................. 349 Customer Support .............................................................................................................................................................................. 349 Reader Response .............................................................................................................................................................................. 350 Product Identification System............................................................................................................................................................. 351 DS39897C-page 8 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY DS39897C-page 9 ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 10 2009 Microchip Technology Inc. ...
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... This document contains device-specific information for the following devices: • PIC24FJ64GB106 • PIC24FJ192GB108 • PIC24FJ128GB106 • PIC24FJ256GB108 • PIC24FJ192GB106 • PIC24FJ64GB110 • PIC24FJ256GB106 • PIC24FJ128GB110 • PIC24FJ64GB108 • PIC24FJ192GB110 • PIC24FJ128GB108 • PIC24FJ256GB110 This expands on the existing line of Microchip‘s 16-bit microcontrollers, combining an expanded peripheral feature set and enhanced computational performance with a new connectivity option: USB On-The-Go ...
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... This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. memory (64 Kbytes for features available on the 2009 Microchip Technology Inc. ...
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... JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) Instruction Set Packages Note 1: Peripherals are accessible through remappable pins. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 64GB106 128GB106 DC – 32 MHz 64K 128K 22,016 44,032 16,384 ...
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... Yes Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 80-Pin TQFP 256GB108 192K 256K 67,072 87,552 2009 Microchip Technology Inc. ...
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... JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) Instruction Set Packages Note 1: Peripherals are accessible through remappable pins. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 64GB110 128GB110 DC – 32 MHz 64K 128K 22,016 44,032 16,384 ...
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... Multiplier (2) MCLR 10-Bit (3) (3) RTCC Comparators ADC SPI UART I2C (3) (3) 1/2/3 1/2/3 1/2/3/4 (1) PORTA 16 (13 I/O) PORTB (16 I/ (1) PORTC (8 I/ (1) PORTD (16 I/O) (1) PORTE (10 I/O) (1) PORTF 16-Bit ALU (9 I/O) 16 (1) PORTG (12 I/O) USB OTG PMP/PSP CTMU 2009 Microchip Technology Inc. ...
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... C3INB 54 68 C3INC 48 60 C3IND 47 59 CLKI 39 49 CLKO 40 50 Legend: TTL = TTL input buffer ANA = Analog level input/output 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP 25 I ANA A/D Analog Inputs ANA 23 I ANA 22 I ANA ...
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... CN39 — — CN40 — — CN41 — 23 CN42 — 24 Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897C-page 18 Input I/O Buffer TQFP Interrupt-on-Change Inputs Schmitt Trigger input buffer C™ C/SMBus input buffer Description 2009 Microchip Technology Inc. ...
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... CN79 — — CN80 — — CN81 — — CN82 — — CTED1 28 34 CTED2 27 33 CTPLS REF Legend: TTL = TTL input buffer ANA = Analog level input/output 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP Interrupt-on-Change Inputs ...
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... O — — — 71 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15 Parallel Master Port Chip Select 2 Strobe/Address Bit 14 — Parallel Master Port Byte Enable Strobe Schmitt Trigger input buffer C™ C/SMBus input buffer Description 2009 Microchip Technology Inc. ...
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... RB13 28 34 RB14 29 35 RB15 30 36 Legend: TTL = TTL input buffer ANA = Analog level input/output 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP 93 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). 94 I/O ...
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... USB Receive Input (from external transceiver). 72 I/O ST PORTD Digital I/ I/O ST PORTE Digital I/ I/O ST 100 — Reference Clock Output Schmitt Trigger input buffer C™ C/SMBus input buffer Description 2009 Microchip Technology Inc. ...
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... RP14 29 35 RP15 — 43 RP16 33 41 RP17 32 40 RP18 11 15 RP19 6 8 Legend: TTL = TTL input buffer ANA = Analog level input/output 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP 87 I/O ST PORTF Digital I/ I/O ST ...
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... JTAG Test Data/Programming Data Input — JTAG Test Data Output JTAG Test Mode Select Input USB OTG ID (OTG mode only — USB Output Enable Control (for external transceiver Schmitt Trigger input buffer C™ C/SMBus input buffer Description 2009 Microchip Technology Inc. ...
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... REF V 9, 25, 41 11, 31, 51 15, 36, 45 USB Legend: TTL = TTL input buffer ANA = Analog level input/output 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Input I/O 100-Pin Buffer TQFP 54 P — USB Voltage, Host mode (5V — USB OTG External Charge Pump Control. ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 26 2009 Microchip Technology Inc. ...
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... REF REF reference for analog modules is implemented Note: The AV and AV pins must always connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 2- MCLR (2) C6 ...
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... The DD may be beneficial. A typical ) and fast signal transitions must IL is replaced for normal run-time EXAMPLE OF MCLR PIN CONNECTIONS R1 R2 MCLR PIC24FXXXX JP C1 and V specifications are met and V specifications are met. IL 2009 Microchip Technology Inc. ...
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... When the regulator is disabled, the V CAP must be tied to a voltage supply at the V Refer to Section 29.0 “Electrical Characteristics” for information on V and DDCORE 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 2- 0.1 0.01 0.001 0.01 Note: Data for Murata GRM21BF50J106ZE01 shown. ...
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... Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSCI ` OSCO GND ` SOSCO SOSC I ` Sec Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC24FJ256GB110 FAMILY If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must modify the appropriate bits during initialization of the ADC module, as follows: • ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 32 2009 Microchip Technology Inc. ...
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... Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY For most instructions, the core is capable of executing a data (or program data) memory read, a working reg- ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle ...
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... Control Control Signals to Various Blocks DS39897C-page 34 Data Bus 16 16 Data Latch PCL Data RAM Address Loop Latch Control Logic RAGU WAGU EA MUX ROM Latch 16 Instruction Reg Hardware Multiplier Register Array Divide Support 16-Bit ALU Peripheral Modules 2009 Microchip Technology Inc. ...
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... W10 W11 W12 W13 W14 W15 22 Registers or bits shaded for PUSH.S and POP.S instructions. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register ...
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... Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39897C-page 36 U-0 U-0 — — (1) R-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1,2) U-0 U-0 R/W-0 — — DC bit 8 R/W-0 R/W-0 R/W bit Bit is unknown 2009 Microchip Technology Inc. ...
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... Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — ...
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... All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 3-2. Description 2009 Microchip Technology Inc. ...
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... Device Config Registers Reserved DEVID (2) Note: Memory areas are not shown to scale. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or data space remapping, as described in Section 4.3 “Interfacing Program and Data Memory Spaces”. ...
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... Word for devices in the FLASH CONFIGURATION WORDS FOR PIC24FJ256GB110 FAMILY DEVICES Program Configuration Memory Word (Words) Addresses 00ABFAh: 22,016 00ABFEh 0157FAh: 44,032 0157FEh 020BFAh: 67,072 020BFEh 02ABFAh: 87,552 02ABFEh PC Address (LSW Address) 0 000000h 000002h 000004h 000006h 2009 Microchip Technology Inc. ...
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... FFFFh Note: Data memory areas are not shown to scale. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PIC24FJ256GB110 family devices implement a total of 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. ...
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... SPI/I C SPI — — — — — — — — CRC — System NVM/PMD — xxA0 xxC0 xxE0 Interrupts — Compare UART I/O — — — USB — — — — PPS — — — — 2009 Microchip Technology Inc. ...
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TABLE 4-3: CPU CORE REGISTERS MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 ...
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TABLE 4-4: ICN REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name CNPD1 0054 CN15PDE CN14PDE CN13PDE CN12PDE CNPD2 0056 CN31PDE CN30PDE CN29PDE CN28PDE (1) (2) (1) (1) CNPD3 0058 CN47PDE CN46PDE CN45PDE CN44PDE CNPD4 005A ...
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TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS — — — INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 U2TXIF U2RXIF INT2IF ...
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TABLE 4-6: TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — ...
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TABLE 4-7: INPUT CAPTURE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 IC1CON2 0142 — — — — IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 — — ICSIDL ...
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TABLE 4-8: OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC1CON1 0190 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OC1CON2 0192 FLTMD FLTOUT FLTTRIEN OCINV OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A — ...
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TABLE 4-8: OUTPUT COMPARE REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 OC8CON1 01D6 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN OCINV OC8RS 01DA OC8R 01DC OC8TMR 01DE OC9CON1 01E0 ...
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TABLE 4-10: UART REGISTER MAPS File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — — ...
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TABLE 4-12: PORTA REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISA 02C0 TRISA15 TRISA14 — — PORTA 02C2 RA15 RA14 — — LATA 02C4 LATA15 LATA14 — — ODCA 02C6 ODA15 ODA14 — ...
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TABLE 4-16: PORTE REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name TRISE 02E0 — — — — PORTE 02E2 — — — — LATE 02E4 — — — — ODCE 02E6 — — — — ...
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TABLE 4-20: ADC REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ...
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TABLE 4-22: USB OTG REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1OTGIR 0480 — — — — U1OTGIE 0482 — — — — U1OTGSTAT 0484 — — — — U1OTGCON 0486 — ...
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TABLE 4-22: USB OTG REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1EP0 04AA — — — — U1EP1 04AC — — — — U1EP2 04AE — — — — U1EP3 04B0 ...
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TABLE 4-24: REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME AMASK3 AMASK2 RTCVAL 0624 RCFGCAL 0626 RTCEN — RTCWREN RTCSYNC HALFSEC Legend: — = unimplemented, ...
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TABLE 4-27: PERIPHERAL PIN SELECT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — INT1R5 INT1R4 RPINR1 0682 — — INT3R5 INT3R4 RPINR2 0684 — — — — RPINR3 0686 — — ...
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TABLE 4-28: SYSTEM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — OSCCON 0742 — COSC2 COSC1 COSC0 CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 OSCTUN 0748 — — — — ...
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... W15 (before CALL) PC<22:16> 000000000 <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 4.3 Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space ...
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... Bits 24 Bits Select 1 PSVPAG 0 8 Bits 23 Bits <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx (1) Data EA<14:0> xxx xxxx xxxx xxxx 0 EA 1/0 16 Bits Bits Byte Select 2009 Microchip Technology Inc. ...
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... FIGURE 4-6: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16> data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. ...
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... PSV Area 800000h 1111’ or 0000h Data EA<14:0> 8000h ...while the lower 15 bits of the EA specify an exact address within the PSV area. FFFFh This corresponds exactly to the same lower 15 bits of the actual program space address. 2009 Microchip Technology Inc. ...
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... Using Table Instruction User/Configuration Space Select 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instruc- tions (192 bytes time, and erase program memory in blocks of 512 instructions (1536 bytes time. Manual” ...
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... A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. 2009 Microchip Technology Inc. ...
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... Memory row program operation (ERASE = operation (ERASE = 1) Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP™ mode only. Refer to device programming specification. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY (1) U-0 U-0 — — ...
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... Initialize in-page EA[15:0] pointer ; Set base address of erase block ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted functions, is shown in 2009 Microchip Technology Inc. ...
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... MOV #LOW_WORD_31, W2 MOV #HIGH_BYTE_31, W3 TBLWTL W2, [W0] TBLWTH W3, [W0] 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY // Address of row to write // Initialize PM Page Boundary SFR // Initialize lower word of address // Set base address of erase block // with dummy latch write // Initialize NVMCON // Block all interrupts with priority <7 ...
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... Initialize lower word of address // Write to address low word // Write to upper byte // Increment address ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; ; ; and wait for completed 2009 Microchip Technology Inc. ...
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... TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); __builtin_tblwth(offset, progDataH); asm(“DISI #5”); __builtin_write_NVM(); 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to ‘ ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 70 2009 Microchip Technology Inc. ...
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... Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. ...
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... SWDTEN bit setting. DS39897C-page 72 (1) U-0 U-0 — — R/W-0, HS R/W-0, HS R/W-0, HS (2) WDTO SLEEP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 R/W-0, HS R/W-0 — CM PMSLP bit 8 R/W-1, HS R/W-1, HS IDLE BOR POR bit Bit is unknown 2009 Microchip Technology Inc. ...
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... BOR MCLR COSC Control bits (OSCCON<14:12>) WDTO SWR 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Setting Event 6.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 6-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire ...
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... T POR PWRT FRC LOCK POR PWRT OST POR PWRT OST LOCK T — PWRT T T PWRT FRC T T PWRT LPRC T T PWRT LOCK PWRT FRC LOCK T T PWRT OST PWRT FRC LOCK — — 2009 Microchip Technology Inc. Notes — ...
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... FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 6.3 Special Function Register Reset States ...
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... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 76 2009 Microchip Technology Inc. ...
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... PIC24FJ256GB110 family devices non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the ...
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... Alternate Interrupt Vector Table (AIVT) 00017Ch 00017Eh 000180h 0001FEh 000200h AIVT Address 000104h Reserved 000106h Oscillator Failure 000108h Address Error 00010Ah Stack Error 00010Ch Math Error 00010Eh Reserved 000110h Reserved 000112h Reserved (1) (1) Trap Source 2009 Microchip Technology Inc. ...
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... Output Compare 6 Output Compare 7 Output Compare 8 Output Compare 9 Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event SPI3 Error SPI3 Event 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Vector AIVT IVT Address Address 13 00002Eh 00012Eh 18 000038h 000138h ...
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... IEC0<3> IPC0<14:12> IEC0<7> IPC1<14:12> IEC0<8> IPC2<2:0> IEC1<11> IPC6<14:12> IEC1<12> IPC7<2:0> IEC4<1> IPC16<6:4> IEC0<11> IPC2<14:12> IEC0<12> IPC3<2:0> IEC4<2> IPC16<10:8> IEC1<14> IPC7<10:8> IEC1<15> IPC7<14:12> IEC5<1> IPC20<6:4> IEC5<2> IPC20<10:8> IEC5<3> IPC20<14:12> IEC5<7> IPC21<14:12> IEC5<8> IPC22<2:0> IEC5<9> IPC22<6:4> IEC5<6> IPC21<10:8> 2009 Microchip Technology Inc. ...
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... See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 — ...
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... Unimplemented: Read as ‘0’ DS39897C-page 82 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown 2009 Microchip Technology Inc. ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — ...
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... Interrupt request has not occurred DS39897C-page 84 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF1IF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 85
... MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 T5IF T4IF ...
Page 86
... Interrupt request has not occurred DS39897C-page 86 R/W-0 R/W-0 R/W-0 OC8IF OC7IF OC6IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC5IF IC6IF bit 8 R/W-0 R/W-0 SPI2IF SPF2IF bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 87
... Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — ...
Page 88
... Unimplemented: Read as ‘0’ DS39897C-page 88 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — CRCIF U2ERIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2009 Microchip Technology Inc. U-0 R/W-0 — LVDIF bit 8 R/W-0 U-0 U1ERIF — bit Bit is unknown ...
Page 89
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 OC9IF SPI3IF SPF3IF ...
Page 90
... Interrupt request not enabled DS39897C-page 90 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF1IE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 91
... Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 10.4 “Peripheral Pin Select” for more information. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 (1) ...
Page 92
... SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. See Section 10.4 “Peripheral Pin Select” for more information. DS39897C-page 92 2009 Microchip Technology Inc. ...
Page 93
... SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 OC8IE OC7IE OC6IE ...
Page 94
... See Section 10.4 “Peripheral Pin Select” for more information. DS39897C-page 94 U-0 U-0 — — U-0 U-0 (1) — — MI2C2IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 SI2C2IE — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 95
... U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 96
... Unimplemented: Read as ‘0’ DS39897C-page 96 R/W-0 R/W-0 R/W-0 OC9IE SPI3IE SPF3IE R/W-0 R/W-0 R/W-0 SI2C3IE U3TXIE U3RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U4TXIE U4RXIE bit 8 R/W-0 U-0 U3ERIE — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 97
... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 T1IP0 — OC1IP2 R/W-0 ...
Page 98
... Unimplemented: Read as ‘0’ DS39897C-page 98 R/W-0 U-0 R/W-1 T2IP0 — OC2IP2 R/W-0 U-0 U-0 IC2IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC2IP1 OC2IP0 bit 8 U-0 U-0 — — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 99
... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 U1RXIP0 — SPI1IP2 R/W-0 ...
Page 100
... Interrupt source is disabled DS39897C-page 100 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 AD1IP0 — U1TXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 U1TXIP1 U1TXIP0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 101
... Unimplemented: Read as ‘0’ bit 2-0 SI2C1P<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 CNIP0 — CMIP2 R/W-0 ...
Page 102
... Interrupt source is disabled DS39897C-page 102 R/W-0 U-0 R/W-1 IC8IP0 — IC7IP2 U-0 U-0 R/W-1 — — INT1IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC7IP1 IC7IP0 bit 8 R/W-0 R/W-0 INT1IP1 INT1IP0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 103
... OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 T4IP0 — OC4IP2 R/W-0 ...
Page 104
... Interrupt source is disabled DS39897C-page 104 R/W-0 U-0 R/W-1 U2TXIP0 — U2RXIP2 R/W-0 U-0 R/W-1 INT2IP0 — T5IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2RXIP1 U2RXIP0 bit 8 R/W-0 R/W-0 T5IP1 T5IP0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 105
... Unimplemented: Read as ‘0’ bit 2-0 SPF2IP<2:0>: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 106
... Unimplemented: Read as ‘0’ DS39897C-page 106 R/W-0 U-0 R/W-1 IC5IP0 — IC4IP2 R/W-0 U-0 U-0 IC3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC4IP1 IC4IP0 bit 8 U-0 U-0 — — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 107
... Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 R/W-1 OC7IP0 — OC6IP2 R/W-0 ...
Page 108
... Interrupt source is disabled DS39897C-page 108 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 PMPIP0 — OC8IP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 OC8IP1 OC8IP0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 109
... SI2C2P<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 R/W-1 — — MI2C2P2 R/W-0 ...
Page 110
... Unimplemented: Read as ‘0’ DS39897C-page 110 U-0 U-0 R/W-1 — — INT4IP2 R/W-0 U-0 U-0 INT3IP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 INT4IP1 INT4IP0 bit 8 U-0 U-0 — — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 111
... RTCIP<2:0>: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 R/W-1 — — RTCIP2 U-0 ...
Page 112
... Unimplemented: Read as ‘0’ DS39897C-page 112 R/W-0 U-0 R/W-1 CRCIP0 — U2ERIP2 R/W-0 U-0 U-0 U1ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U2ERIP1 U2ERIP0 bit 8 U-0 U-0 — — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 113
... CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — U-0 ...
Page 114
... Unimplemented: Read as ‘0’ DS39897C-page 114 R/W-0 U-0 R/W-1 U3TXIP0 — U3RXIP2 R/W-0 U-0 U-0 U3ERIP0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 U3RXIP1 U3RXIP0 bit 8 U-0 U-0 — — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 115
... Unimplemented: Read as ‘0’ bit 2-0 SI2C3P<2:0>: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 R/W-0 R/W-1 U4ERIP0 — USB1IP2 R/W-0 ...
Page 116
... Interrupt source is disabled DS39897C-page 116 R/W-0 U-0 R/W-1 SPI3IP0 — SPF3IP2 R/W-0 U-0 R/W-1 U4TXIP0 — U4RXIP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPF3IP1 SPF3IP0 bit 8 R/W-0 R/W-0 U4RXIP1 U4RXIP0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 117
... Unimplemented: Read as ‘0’ bit 2-0 OC9IP<2:0>: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — — R/W-0 ...
Page 118
... Interrupt vector pending is number 8 DS39897C-page 118 U-0 R-0 R-0 — ILR3 ILR2 R-0 R-0 R-0 VECNUM4 VECNUM3 VECNUM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-0 R-0 ILR1 ILR0 bit 8 R-0 R-0 VECNUM1 VECNUM0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 119
... ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 120
... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 120 2009 Microchip Technology Inc. ...
Page 121
... Secondary Oscillator SOSCO SOSCEN Enable SOSCI Oscillator 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY • An on-chip USB PLL block to provide a stable, 48 MHz clock for the USB module as well as a range of frequency options for the system clock • Software-controllable switching between various clock sources • ...
Page 122
... FCKSM<1:0> are both programmed (‘00’). Oscillator Source POSCMD<1:0> Internal 11 Internal xx Internal 11 Secondary 11 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal 11 Internal 11 bits, POSCMD<1:0> (Configuration Configuration bits (Configuration FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 011 011 010 010 010 1 001 1 000 2009 Microchip Technology Inc. ...
Page 123
... IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL clock mode is selected. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY The OSCCON register (Register 8-1) is the main con- trol register for the oscillator ...
Page 124
... The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: Also resets to ‘0’ during any valid clock switch or whenever a non PLL clock mode is selected. DS39897C-page 124 (2) (3) 2009 Microchip Technology Inc. ...
Page 125
... MHz (divide-by-1) bit 5-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. 2: This setting is not allowed while the USB module is enabled. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 (1) DOZE0 ...
Page 126
... FNOSCx Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled held at ‘0’ at all times. U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 R/W-0 (1) (1) (1) TUN2 TUN1 TUN0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 127
... In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY A recommended code sequence for a clock switch includes the following: 1. Disable interrupts during the OSCCON register unlock and write sequence ...
Page 128
... HSPLL, ECPLL 5 (100) HSPLL, ECPLL 4 (011) HSPLL, ECPLL 3 (010) HSPLL, ECPLL 2 (001) ECPLL, XTPLL 1 (000) ECPLL, XTPLL 48 MHz Clock for USB Module PLL Output 4 for System Clock 10 CPDIV<1:0> 2009 Microchip Technology Inc. ...
Page 129
... They may still be useful in cases where other power levels of operation are desirable and the USB module is not needed (e.g., the application is in Sleep and waiting for bus attachment). 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 8.6 Reference Clock Output In addition to the CLKO output (F ...
Page 130
... Unimplemented: Read as ‘0’ DS39897C-page 130 R/W-0 R/W-0 R/W-0 ROSEL RODIV3 RODIV2 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RODIV1 RODIV0 bit 8 U-0 U-0 — — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 131
... Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes said to “ ...
Page 132
... By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows possible further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications. 2009 Microchip Technology Inc. ...
Page 133
... CK WR PORT Data Latch Read LAT Read PORT 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled ...
Page 134
... PORTF<13:12>, PORTF<8>, PORTF<5:1> PORTG<15:12>, PORTG<1:0> Note 1: Not all port pins shown here are imple- mented on 64-pin and 80-pin devices. Refer to Section 1.0 “Device Overview” to confirm which ports are available in specific devices. 2009 Microchip Technology Inc. (1) Description input DD , useful for ...
Page 135
... Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 10.4 Peripheral Pin Select A major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins ...
Page 136
... Table 10-3). Because of the mapping technique, the list of peripher- als for output mapping also includes a null value of ‘000000’. This permits any given pin to remain discon- nected from the output of any of the pin-selectable peripherals peripheral to a 2009 Microchip Technology Inc. ...
Page 137
... UART2 Clear To Send UART2 Receive UART3 Clear To Send UART3 Receive UART4 Clear To Send UART4 Receive Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Register INT1 RPINR0 INT2 RPINR1 INT3 RPINR1 ...
Page 138
... Output Compare 8 U3TX UART3 Transmit (3) U3RTS UART3 Request To Send U4TX UART4 Transmit (3) U4RTS UART4 Request To Send SDO3 SPI3 Data Output SCK3OUT SPI3 Clock Output SS3OUT SPI3 Slave Select Output OC9 Output Compare 9 C3OUT Comparator 3 Output (unused) 2009 Microchip Technology Inc. Null NC ...
Page 139
... Total 64-pin 28 80-pin 31 100-pin 32 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 10.4.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these reg- isters, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON< ...
Page 140
... Configure Input Functions (Table 9-1)) // Assign U1RX To Pin RP0 RPINR18bits.U1RXR = 0; // Assign U1CTS To Pin RP1 RPINR18bits.U1CTSR = 1; // Configure Output Functions (Table 9-2) // Assign U1TX To Pin RP2 RPOR1bits.RP2R = 3; // Assign U1RTS To Pin RP3 RPOR1bits.RP3R = 4; // Lock Registers __builtin_write_OSCCONL(OSCCON | 0x40); CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS 2009 Microchip Technology Inc. ...
Page 141
... INT3R<5:0>: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Note: Input and output register values can only be changed if IOLOCK (OSCCON<6> ...
Page 142
... T2CKR4 T2CKR3 T2CKR2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-1 R/W-1 INT4R1 INT4R0 bit Bit is unknown R/W-1 R/W-1 T3CKR1 T3CKR0 bit 8 R/W-1 R/W-1 T2CKR1 T2CKR0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 143
... IC2R<5:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 T5CKR4 ...
Page 144
... IC5R4 IC5R3 IC5R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC4R1 IC4R0 bit 8 R/W-1 R/W-1 IC3R1 IC3R0 bit Bit is unknown R/W-1 R/W-1 IC6R1 IC6R0 bit 8 R/W-1 R/W-1 IC5R1 IC5R0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 145
... OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 IC8R4 ...
Page 146
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 IC9R1 IC9R0 bit 8 U-0 U-0 — — bit Bit is unknown R/W-1 R/W-1 U3RXR1 U3RXR0 bit 8 U-0 U-0 — — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 147
... U2CTSR<5:0>: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR<5:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 U1CTSR4 ...
Page 148
... SS1R4 SS1R3 SS1R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 SCK1R1 SCK1R0 bit 8 R/W-1 R/W-1 SDI1R1 SDI1R0 bit Bit is unknown R/W-1 R/W-1 U3CTSR1 U3CTSR0 bit 8 R/W-1 R/W-1 SS1R1 SS1R0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 149
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-1 R/W-1 R/W-1 SCK2R4 SCK2R3 SCK2R2 ...
Page 150
... SDI3R4 SDI3R3 SDI3R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 U4CTSR1 U4CTSR0 bit 8 R/W-1 R/W-1 U4RXR1 U4RXR0 bit Bit is unknown R/W-1 R/W-1 SCK3R1 SCK3R0 bit 8 R/W-1 R/W-1 SDI3R1 SDI3R0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 151
... Peripheral output number n is assigned to pin, RP1 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP0R<5:0>: RP0 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP0 (see Table 10-3 for peripheral function numbers) 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — ...
Page 152
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 R/W-0 RP3R1 RP3R0 bit 8 R/W-0 R/W-0 R/W-0 RP2R1 RP2R0 bit Bit is unknown R/W-0 R/W-0 R/W-0 (1) (1) (1) RP5R1 RP5R0 bit 8 R/W-0 R/W-0 R/W-0 RP4R1 RP4R0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 153
... Peripheral output number n is assigned to pin, RP9 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP8R<5:0>: RP8 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP8 (see Table 10-3 for peripheral function numbers) 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP7R4 ...
Page 154
... RP12R4 RP12R3 RP12R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP11R1 RP11R0 bit 8 R/W-0 R/W-0 RP10R1 RP10R0 bit Bit is unknown R/W-0 R/W-0 RP13R1 RP13R0 bit 8 R/W-0 R/W-0 RP12R1 RP12R0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 155
... Peripheral output number n is assigned to pin, RP17 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP16R<5:0>: RP16 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP16 (see Table 10-3 for peripheral function numbers) 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 (1) ...
Page 156
... RP20R4 RP20R3 RP20R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP19R1 RP19R0 bit 8 R/W-0 R/W-0 RP18R1 RP18R0 bit Bit is unknown R/W-0 R/W-0 RP21R1 RP21R0 bit 8 R/W-0 R/W-0 RP20R1 RP20R0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 157
... Peripheral output number n is assigned to pin, RP25 (see Table 10-3 for peripheral function numbers) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP24R<5:0>: RP24 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP24 (see Table 10-3 for peripheral function numbers) 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 RP23R4 ...
Page 158
... RP28R4 RP28R3 RP28R2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RP27R1 RP27R0 bit 8 R/W-0 R/W-0 RP26R1 RP26R0 bit Bit is unknown R/W-0 R/W-0 RP29R1 RP29R0 bit 8 R/W-0 R/W-0 RP28R1 RP28R0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 159
... RP30R<5:0>: RP30 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP30 (see Table 10-3 for peripheral function numbers) Note 1: Unimplemented on 64-pin and 80-pin devices; read as ‘0’. 2: Unimplemented on 64-pin devices; read as ‘0’. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 R/W-0 (1) ...
Page 160
... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 160 2009 Microchip Technology Inc. ...
Page 161
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Figure 11-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1). 2. Select the timer prescaler ratio using the TCKPS<1:0> bits. ...
Page 162
... DS39897C-page 162 (1) U-0 U-0 — — R/W-0 U-0 R/W-0 TCKPS0 — TSYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) U-0 U-0 U-0 — — — bit 8 R/W-0 U-0 TCS — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 163
... Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 bit (T2CON<3> or T4CON<3> = 1). ...
Page 164
... The ADC Event Trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS39897C-page 164 1x Gate Sync PR3 PR2 (PR5) (PR4) Comparator LSB TMR2 TMR3 (TMR4) (TMR5 TMR3HLD (TMR5HLD) TCKPS<1:0> 2 TON Prescaler 1, 8, 64, 256 (2) TGATE (2) TCS Sync 2009 Microchip Technology Inc. ...
Page 165
... Equal Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information. 2: The ADC Event Trigger is available only on Timer3. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 1x Gate Sync 01 ...
Page 166
... DS39897C-page 166 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS0 T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /2) (3) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 (2) — TCS — bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 167
... If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 10.4 “Peripheral Pin Select” for more information. 3: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 (1) — ...
Page 168
... PIC24FJ256GB110 FAMILY NOTES: DS39897C-page 168 2009 Microchip Technology Inc. ...
Page 169
... Reset Trigger and Sync Sources Note 1: The ICx inputs must be assigned to an available RPn pin before use. Please see Section 10.4 “Peripheral Pin Select” for more information. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 13.1 General Operating Modes 13.1.1 SYNCHRONOUS AND TRIGGER ...
Page 170
... ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module’s ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (perform automatically by hardware). 2009 Microchip Technology Inc. modules Trigger or ...
Page 171
... Input capture module turned off Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select”. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 R/W-0 ICTSEL2 ...
Page 172
... DS39897C-page 172 U-0 U-0 — — R/W-0 R/W-1 SYNCSEL4 SYNCSEL3 SYNCSEL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) (1) U-0 U-0 R/W-0 — — IC32 bit 8 R/W-1 R/W-0 R/W-1 SYNCSEL1 SYNCSEL0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 173
... Compare or PWM events are generated each time a match between the internal counter and one of the period registers occurs. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module’ ...
Page 174
... OCxCON1 OCxCON2 OCxR Match Event Comparator OCxTMR Reset Match Event Comparator OCxRS the time base source with the OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 (1) OCx Pin OC Output and Fault Logic OCFA/OCFB OCx Interrupt 2009 Microchip Technology Inc. ...
Page 175
... Single Compare modes, and after each OCxRS match in Double Compare modes. Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuous pulse events continue indefinitely until terminated. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 14.3 Pulse-Width Modulation (PWM) Mode registers ...
Page 176
... Table 14-1 and Table 14-2 show example PWM frequencies and resolutions for a device operating at 4 MIPS and 10 MIPS, respectively. OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 OCx Pin OC Output and Fault Logic OCFA/OCFB OCx Interrupt 2009 Microchip Technology Inc. ...
Page 177
... PWM Frequency 30.5 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 Note 1: Based /2, Doze mode and PLL are disabled. CY OSC 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY ( F CY log 10 F • (Timer Prescale Value) PWM log ( /2, Doze mode and PLL are disabled. ...
Page 178
... OCTSEL1 OCTSEL0 R/W-0, HCS R/W-0 R/W-0 (1) OCFLT0 TRIGMODE OCM2 HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (2) U-0 U-0 — — bit 8 R/W-0 R/W-0 (1) (1) OCM1 OCM0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 179
... Output compare peripheral x connected to OCx pin Note 1: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY R/W-0 U-0 U-0 OCINV — ...
Page 180
... Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. 2: Use these inputs as trigger sources only and never as sync sources. DS39897C-page 180 (1) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (1) (1) (1) (1) (1) (1) (1) (1) (1) 2009 Microchip Technology Inc. ...
Page 181
... Enhanced Buffer mode. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY The SPI serial interface consists of four pins: • SDIx: Serial Data Input • ...
Page 182
... Clear the SPIROV bit (SPIxSTAT<6>). 7. Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer Write SPIxBUF 16 Internal Data Bus registers with MSTEN 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock 2009 Microchip Technology Inc. ...
Page 183
... SDOx bit0 SDIx SPIxSR Transfer 8-Level FIFO Receive Buffer SPIxBUF Read SPIxBUF 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. Clear the SPIxBUF register using interrupts: a) Clear the SPIxIF bit in the respective IFS register ...
Page 184
... U-0 U-0 — — SPIBEC2 R/W-0 R/W-0 SISEL2 SISEL1 HS = Hardware settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-0 R-0 R-0 SPIBEC1 SPIBEC0 bit 8 R/W-0 R-0 R-0 SISEL0 SPITBF SPIRBF bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 185
... Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 10.4 “Peripheral Pin Select” for more information. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY DS39897C-page 185 ...
Page 186
... R/W-0 R/W-0 R/W-0 (1) (2) DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE2 SPRE1 SPRE0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) R/W-0 R/W-0 (3) SMP CKE bit 8 R/W-0 R/W-0 PPRE1 PPRE0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 187
... Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY U-0 U-0 U-0 — — ...
Page 188
... SDIx SDOx Serial Clock SCKx SCKx (1) (1) SSx SSx SSEN (SPIxCON1<7> MSTEN (SPIxCON1<5> and SPIBEN (SPIxCON2<0> (SPIxRXB) Shift Register (SPIxSR) LSb (SPIxTXB) SPIx Buffer (2) (SPIxBUF) Shift Register (SPIxSR) MSb LSb 8-Level FIFO Buffer SPIx Buffer (2) (SPIxBUF) 2009 Microchip Technology Inc. ...
Page 189
... FIGURE 15-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Master) FIGURE 15-8: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PROCESSOR 2 SDOx SDIx SDIx SDOx Serial Clock SCKx ...
Page 190
... Microchip Technology Inc. ...
Page 191
... Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address • Automatic SCL A block diagram of the module is shown in Figure 16-1. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.1 Communicating as a Master in a Single Master Environment The details of sending a message in Master mode depends on the communications protocol for the device being communicated with ...
Page 192
... Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSB Reload Control Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read 2009 Microchip Technology Inc. ...
Page 193
... The address bits listed here will never cause an address match, independent of address mask settings. 2: Address will be Acknowledged only if GCEN = 1. 3: Match on this address can only occur on the upper byte in 10-Bit Addressing mode. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.3 Slave Address Masking The I2CxMSK register (Register 16-3) designates address bit positions as “ ...
Page 194
... R/W-0, HC R/W-0, HC R/W-0, HC ACKEN RCEN PEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C pins are controlled by port functions Slave slave slave) R/W-0 R/W-0 DISSLW SMEN bit 8 R/W-0, HC R/W-0, HC RSEN SEN bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 195
... Repeated Start condition not in progress bit 0 SEN: Start Condition Enabled bit (when operating Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2 C master. Applicable during master receive master ...
Page 196
... S R Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared slave) R-0, HSC R-0, HSC GCSTAT ADD10 bit 8 R-0, HSC R-0, HSC RBF TBF bit 0 HSC = Hardware Settable/Clearable bit x = Bit is unknown C module is busy 2009 Microchip Technology Inc. ...
Page 197
... Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2 C slave device address byte. ...
Page 198
... Disable masking for bit x; bit match required in this position DS39897C-page 198 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 AMSK4 AMSK3 AMSK2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 AMSK9 AMSK8 bit 8 R/W-0 R/W-0 AMSK1 AMSK0 bit Bit is unknown 2009 Microchip Technology Inc. ...
Page 199
... Note: The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 10.4 “Peripheral Pin Select” for more information. 2009 Microchip Technology Inc. PIC24FJ256GB110 FAMILY • Fully Integrated Baud Rate Generator with 16-Bit Prescaler • ...
Page 200
... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. /(16 * 65536). UART BAUD RATE WITH (1,2) BRGH = • (UxBRG + – • Baud Rate denotes the instruction cycle clock = F /2, Doze mode CY OSC /4 CY (1) 2009 Microchip Technology Inc. ...