CDB4382A Cirrus Logic Inc, CDB4382A Datasheet - Page 30

• Manufacturer Part Number: CDB4382A
• Description: Eval Bd 114dB 192kHz 8Chn DAC W/DSD Supt
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4382A

• Number Of Dac's: 8
• Number Of Bits: 24
• Outputs And Type: 8, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4382A
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS4382A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1524

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4.14.3 SPI Mode
4.14.2.2 I²C Read
To read from the device, follow the procedure below while adhering to the Control Port Switching Speci-
fications.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-
5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to initiate
4.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-
tions in
1. Bring CS low.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial Control Port clock, CCLK
(see
is used to control SPI writes to the Control Port. When the device detects a high-to-low transition on the
AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
pointed to by the MAP. The MAP register will contain the address of the last register written to the
MAP, or the default address (see
device.
tinue providing a clock and issue an ACK after each byte until all the desired registers are read; then
initiate a STOP condition to the bus.
a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C Write
instructions followed by step 1 of the I²C Read section. If no further reads from other registers are de-
sired, initiate a STOP condition to the bus.
are written, then bring CS high.
Figure 19
Section
S C L
S D A
N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P .
for the clock-to-data relationship). There is no AD0 pin. Pin CS is the chip select signal and
S ta rt
2.
0 01 1 00
Section
Figure 18. Control Port Timing, I²C Mode
A D D R
AD 0
4.14.1) is set to 1, repeat the previous step until all the desired registers
Section
R /W
A C K
4.14.1) if an I²C read is the first operation performed on the
D AT A
1-8
N o te 1
A C K
D A TA
1-8
A C K
S top
CS4382A
DS618F2