CDB4382A Cirrus Logic Inc, CDB4382A Datasheet - Page 35

• Manufacturer Part Number: CDB4382A
• Description: Eval Bd 114dB 192kHz 8Chn DAC W/DSD Supt
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4382A

• Number Of Dac's: 8
• Number Of Bits: 24
• Outputs And Type: 8, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4382A
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CS4382A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1524

DS618F2
6.3
6.3.1
DIF2
SZC1
0
0
0
0
1
1
1
1
7
1
Mode Control 3 (Address 03h)
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
master clock-to-DSD-data-rate is defined by the Digital Interface Format pins.
Soft Ramp and Zero Cross Control (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or
muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change
will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz
sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently
monitored and implemented for each channel.
DIF1
0
0
1
1
0
0
1
1
SZC0
6
0
Table 6. Digital Interface Formats - DSD Mode
DIFO
SNGLVOL
0
1
0
1
0
1
0
1
5
0
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
RMP_UP
4
0
MUTEC+/-
DESCRIPTION
3
0
AMUTE
2
1
Reserved
1
0
CS4382A
MUTEC
0
0
35