COP8SAC720M8 National Semiconductor, COP8SAC720M8 Datasheet - Page 17

• Manufacturer Part Number: COP8SAC720M8
• Description: -LIFETIME BUYS TIL 06/05
• Manufacturer: National Semiconductor

Specifications of COP8SAC720M8

• Rohs Compliant: NO

6.0 Functional Description
6.7 RESET
The device is initialized when the RESET pin is pulled low or
the On-chip Power-On Reset is enabled.
The following occurs upon initialization:
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in-
hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error follow-
ing reset if the clock has not reached the minimum specified
Port L: TRISTATE
Port C: TRISTATE
Port G: TRISTATE
Port F: TRISTATE
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR: UNAFFECTED after RESET with power already
T1CNTRL: CLEARED
Accumulator, Timer 1:
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
B and X Pointers:
RAM:
WATCHDOG (if enabled):
applied
RANDOM after RESET at power-on
RANDOM after RESET with crystal clock option
(power already applied)
UNAFFECTED after RESET with R/C clock option
(power already applied)
RANDOM after RESET at power-on
Initialized to RAM address 02F Hex (devices with
64 bytes of RAM), or initialized to
RAM address 06F Hex (devices with
128 bytes of RAM).
UNAFFECTED after RESET with power
already applied
RANDOM after RESET at power-on
UNAFFECTED after RESET with power already
applied
RANDOM after RESET at power-on
FIGURE 8. Reset Logic
C
clock cycles. The Clock Monitor bit
DS012838-13
(Continued)
17
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
at which time the G1 output will go high.
6.7.1 External Reset
The RESET input when pulled low initializes the device. The
RESET pin must be held low for a minimum of one instruc-
tion cycle to guarantee a valid reset. During Power-Up initial-
ization, the user must ensure that the RESET pin is held low
until the device is within the specified V
circuit on the RESET pin with a delay 5 times (5x) greater
than the power supply rise time or 15 µs whichever is
greater, is recommended. Reset should also be wide enough
to ensure crystal start-up upon Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
A recommended reset circuit for this deviced is shown in Fig-
ure 9 .
RC
6.7.2 On-Chip Power-On Reset
The on-chip reset circuit is selected by a bit in the ECON reg-
ister. When enabled, the device generates an internal reset
as V
circuitry is able to detect both fast and slow rise times on V
(V
Under no circumstances should the RESET pin be allowed
to float. If the on-chip Power-On Reset feature is being used,
RESET pin should be connected directly to V
of the power-on reset detector will always preset the Idle
timer to 0FFF(4096 t
generated.
If the Power-On Reset feature is enabled, the internal reset
will not be turned off until the Idle timer underflows. The inter-
nal reset will perform the same functions as external reset.
The user is responsible for ensuring that V
mum level for the operating frequency within the 4096 t
ter the underflow, the logic is designed such that no addi-
tional internal resets occur as long as V
2.0V.
Note: While the POR feature of the COP8SAx was never intended to function
CC
>
CC
5x power supply rise time or 15 µs, whichever is greater.
as a brownout detector, there are certain constraints of this block that
the system designer must address to properly recover from a brownout
condition. This is true regardless of whether the internal POR or the
external reset feature is used.
A brownout condition is reached when V
the minimum operating conditions of the device. The minimum guaran-
teed operating conditions are defined as V
V
is stopped) operation.
When using either the external reset or the POR feature to recover
from a brownout condition, V
nal reset must be applied whenever it goes below the minimum oper-
ating conditions as stated above.
FIGURE 9. Reset Circuit Using External Reset
rise time between 10 ns and 50 ms).
CC
rises to a voltage level above 2.0V. The on-chip reset
= 2.7V
@
4 MHz, or V
C
). At this time, the internal reset will be
CC
CC
= 2.0V during HALT mode (or when CKI
C
must be lowered to 0.25V or an exter-
–32 t
C
CC
clock cycles following
CC
of the device goes below
CC
CC
= 4.5V
DS012838-14
CC
voltage. An R/C
remains above
CC
is at the mini-
@
. The output
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10 MHz CKI,
C
. Af-
CC