CS61584A-IQ5Z Cirrus Logic Inc, CS61584A-IQ5Z Datasheet - Page 43

• Manufacturer Part Number: CS61584A-IQ5Z
• Description: IC,Line Interface,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61584A-IQ5Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PD1, PD2 - Power Down [Hardware mode] (PLCC pins 24, 45; TQFP pins 15, 34)
ZTX1 - Driver Tristate [Host mode - serial port]
ZTX2 - (PLCC pins 24, 45; TQFP pins 15, 34)
RESET - Reset (PLCC pin 35; TQFP pin 25)
RLOOP1, RLOOP2 - Remote Loopback [Hardware Mode] (PLCC pins 7, 6; TQFP pin 63, 62)
TAOS1 - Transmit All Ones Select [Hardware Mode]
TAOS2 - (PLCC pins 4, 3; TQFP pins 60, 59)
Interface
AD7, AD6, AD5, AD4 - Address/Data Bus [Host mode - parallel port]
AD3, AD2, AD1, AD0 - (PLCC pins 63-66, 2-5; TQFP pins 51-54, 58-61)
ALE (AS) - Address Latch Enable (Address Strobe) [Host mode - parallel port] (PLCC pin 62;
TQFP pin 50)
BTS - Bus Type Select [Host mode - parallel port] (PLCC pin 52; TQFP pin 41)
CS - Chip Select [Host mode] (PLCC pin 8; TQFP pin 64)
DS261PP5
DS261F1
Setting PD high places the channel in a low power, inactive state. Power down forces the transmitter,
receiver, and jitter attenuator to the reset state. All device outputs are forced to a high impedance state
to facilitate circuit board testing.
Setting ZTX high causes the driver at TTIP and TRING to be placed in a tristate (high-impedance)
condition.
A device reset is selected by setting the RESET pin high for a minimum of 200 ns. The reset function
requires less than 20 ms to complete. The control logic and register set are initialized and LOS is set
high. The RESET pin should be set low for normal operation.
A remote loopback of the channel is selected when RLOOP is high. The data received from the line
interface at RTIP and RRING is looped back through the jitter attenuator (if enabled) and retransmitted
on TTIP and TRING. Data recovered from RTIP and RRING continues to be output on RPOS/RNEG
(RDATA). Data input on TPOS/TNEG (TDATA) is ignored.
When the RLOOP and TAOS pins are both high, local loopback #1 is invoked along with transmit all
ones for the selected channel. The receive input at RTIP and RRING is ignored.
Setting TAOS high causes continuous ones to be transmitted on the line interface at the frequency
determined by REFCLK.
When the RLOOP and TAOS pins are both high, local loopback #1 is invoked along with transmit all
ones for the selected channel. The receive input at RTIP and RRING is ignored.
The 8-bit, multiplexed address/data bus.
The address present on the address/data bus is latched on the falling edge of this signal.
This pin controls the function of the RD(DS), ALE(AS), and WR(R/W) pins. Intel bus timing is selected
when BTS is low. Motorola bus timing is selected when BTS is high and the pin function is listed in
parenthesis "( )".
This pin must be low in order to access the serial or parallel port of the device.
DS261PP5
CS61584A
CS61584A
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